Journal Article10.1109/TETC.2016.2585046
Hardware Trojan Detection in Behavioral Intellectual Properties (IP's) Using Property Checking Techniques
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TL;DR: This work introduces a fully automatic method to detect the presence of HW Trojans in third party behavioral IPs (3PBIPs) using formal verification methods and performs High-Level Synthesis on these IPs and re-constructing the C code in order to perform the verification on them.
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Abstract: This work introduces a fully automatic method to detect the presence of HW Trojans in third party behavioral IPs (3PBIPs) using formal verification methods. In particular, property checking at the behavioral level. Some state of the art High-Level Synthesis (HLS) tools now also include advanced formal verification tools. This work leverages these tools to detect the malicious alteration of 3PIPs when no golden reference IP is available. This work has also been extended to detect HW Trojans built into encrypted 3PBIPs by performing High-Level Synthesis on these IPs and re-constructing the C code in order to perform the verification on them. We present three case studies of two of the most typical HW Trojans with different trigger and payload mechanisms. The first leads to the malfunction of the IP, the second leaks information while the third leads to the denial of service. In all three cases, our proposed method was able to detect the HW Trojan in a fully automatic way.
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Citations
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
TL;DR: An overview of hardware security and trust from the perspectives of threats, countermeasures, and design tools is presented to motivate hardware designers and electronic design automation tool developers to consider the new challenges and opportunities of incorporating an additional dimension of security into robust hardware design, testing, and verification.
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis
TL;DR: This letter discusses extensions to HLS tools for creating secure heterogeneous architectures for system-on-chip architectures.
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Ten years of hardware Trojans: a survey from the attacker's perspective
TL;DR: The authors attempt to make a review of the hardware Trojan design and implementations in the last decade and also provide an outlook, focusing on the attacker's methods, capabilities, and challenges when the attacker designs and implements a hardware Trojan.
Hardware Trojans in Chips: A Survey for Detection and Prevention.
TL;DR: A survey of HTs is presented, which shows the threatens of chips, the state-of-the-art preventing and detecting techniques, and the development trends in hardware security are highlighted.
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A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms
TL;DR: Experimental results show that even under big measurement errors, the proposed framework for HT detection gets quite high HT detection rates with low measurement cost.
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References
A Survey of Hardware Trojan Taxonomy and Detection
TL;DR: A classification of hardware Trojans and a survey of published techniques for Trojan detection are presented.
•Book
High-Level Synthesis: from Algorithm to Digital Circuit
Philippe Coussy,Adam Morawiec +1 more
- 10 Oct 2008
TL;DR: This book presents an excellent collection of contributions addressing different aspects of high-level synthesis from both industry and academia, and should be on each designers and CAD developers shelf.
433
Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition
TL;DR: A novel framework for facilitating the acquisition of provably trustworthy hardware intellectual property (IP) that draws upon research in the field of proof-carrying code (PCC) to allow for formal yet computationally straightforward validation of security-related properties by the IP consumer.
175
S2CBench : synthesizable systemc benchmark suite for high-level synthesis
TL;DR: This letter presents a benchmark suite, which complies with the latest Synthesizable SystemC standard, called S2CBench, which allows an easy comparison of not only quality of results (QoR) of the different HLS tools under review, but also to test their completeness.
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