Patent
Flash memory device and operation method
Nam Kyeong Kim,Ju Yeab Lee +1 more
- 09 Jul 2009
4
TL;DR: In this paper, a flash memory device for narrowing a threshold value voltage distribution of programmed memory cells, and an operation method for narrowing the threshold value distribution of memory cells is proposed.
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Abstract: PROBLEM TO BE SOLVED: To provide a flash memory device for narrowing a threshold value voltage distribution of programmed memory cells, and to provide an operation method. SOLUTION: The flash memory device includes: a plurality of memory cell blocks including noble cells; a control unit for generating a block selection signal according to an address signal, and an operation control signal according to a command signal; a program speed calculation section for determining a level of an initial program voltage applied by ISPP program operation based on a threshold value voltage detected after the program operation of the noble cell; a voltage generation part for generating an operation voltage including the initial program voltage of the level determined by the program speed calculation section according to the operation control signal; and a block selection section for transmitting the operation voltage to the memory cell block corresponding to the block selection signal among the plurality of memory cell blocks. COPYRIGHT: (C)2009,JPO&INPIT
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Citations
Patent
Nonvolatile semiconductor memory device and writing method thereof
Senoo Shingen,Arakawa Hideki,Shirata Riichiro +2 more
- 17 Jul 2014
TL;DR: In this paper, a nonvolatile memory cell array and a control circuit that controls writing to the memory array are used to obtain high-speed rewriting characteristics by minimizing variations in a threshold voltage distribution after programming.
1
Patent
Semiconductor storage device and method of writing thereto
芳英 甲斐,Yoshihide Kai +1 more
- 01 Aug 2016
TL;DR: In this article, a memory cell consisting of a control electrode (121), a floating electrode (123), a source (124), and a drain (125) is used for writing data to the memory cell.
Patent
Semiconductor memory device for improving high temperature data retention
Senoo Makoto,Sudo Naoaki +1 more
- 28 May 2019
TL;DR: In this paper, a flash memory includes an erasing element erasing a selected storage cell in a storage cell array in order to improve high-temperature data retention in a semiconductor memory device.
Patent
Semiconductor storage device and writing method for the same
芳英 甲斐,Yoshihide Kai +1 more
- 05 Aug 2015
TL;DR: In this article, a semiconductor storage device has a memory cell consisting of a switch 30 connecting the control electrode and the drain 125, a source driver 14 applying a prescribed voltage to the source 124, a current source 20 configured to be connected to the current source, and a drain driver 16 applying a voltage controlled based on the voltage applied between the control node and the source.
References
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Noboru Shibata,Tomoharu Tanaka +1 more
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TL;DR: In this paper, a memory cell array has a first and a second storage area, the first storage area has a memory elements selected by an address signal, and the second storage is a control circuit with a fuse element.
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Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells
Masaaki Higashitani
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TL;DR: In this article, the memory cells of a nonvolatile memory system are changed during erase operations in order to equalize the erase behavior of select memory cells with other memory cells that are being concurrently erased.
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Patent
Nonvolatile semiconductor memory device
Yasue Yamamoto,Masanori Shirahama,Yasuhiro Agata,Toshiaki Kawasaki +3 more
- 02 Feb 2005
TL;DR: In this paper, a nonvolatile semiconductor memory device storing data by accumulating charges in a floating gate, memory units, each of which includes a first MOS transistor as a read device, a bit cell composed of a first capacitor as a capacitance coupling device and a second capacitor as an erase device, are arranged in array.
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Patent
Nonvolatile semiconductor memory and its test method
Kenichi Imamiya,Koichi Kawai +1 more
- 11 Jul 2003
TL;DR: In this paper, a nonvolatile memory cell array, a write circuit which repeatedly executes a write and a verification, and a write voltage control circuit, is disclosed, which comprises a first binary counter which counts a first clock signal supplied every time the verification fails and supplies output data to the write circuit, a first register which stores data for setting the number of erases and verifications, a second binary counter, which is reset using a first timing, counts a second clock signal provided if a verify write executed on the target write unit fails, an accumulative value storage circuit which
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Patent
Write method for nonvolatile semiconductor storage device and recording medium
Kentaro Neshiba,賢太郎 根芝 +1 more
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