Patent
DMA controller having programmable channel priority
John A. Hayden,Gregory T. Koker +1 more
- 25 Feb 2004
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TL;DR: In this paper, a DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus, a memory DMA stream, including a memory destination channel and a memory source channel, for transferring data on the first and second memory access buses, respectively.
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Abstract: A DMA controller includes at least one peripheral DMA channel for handling DMA transfers on a peripheral access bus; at least one memory DMA stream, including a memory destination channel and a memory source channel, for handling DMA transfers on first and second memory access buses; first and second address computation units for computing updated memory addresses for DMA transfers; and first and second memory pipelines for supplying memory addresses to the first and second memory access buses, respectively, and for transferring data on the first and second memory access buses. The DMA controller further includes a prioritizer configured to map DMA requests from different DMA requesters to the peripheral channels in response to programmable mapping information.
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Citations
Patent
Portable electronic device
Ishibashi Norio
- 23 Jun 2010
TL;DR: In an IC card, an operating system manages the access order of each channel for each file using a channel management table as mentioned in this paper, which stores, as an access order, an order that each logical channel has set a file in a current state.
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Patent
Concurrent read response acknowledge enhanced direct memory access unit
Sanjive Agarwala,Kyle Castille,Quang-Dieu An +2 more
- 10 May 2006
TL;DR: In this article, the authors propose to remove channel prioritization to improve the EDMA inbound and outbound data flow by storing read data in the write buffer and acknowledging the port read response concurrently across all channels.
5
Patent
Facilitating sequential data transformations via direct memory access
Kilsdonk Daniel
- 05 May 2020
TL;DR: A direct memory access (DMA) device provides for transforming source data as it is transferred to a destination memory space as mentioned in this paper, which can encompass a range of arithmetic logic unit (ALU) operations.
References
Patent
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Robert C. Solomon,Jeffrey A. Brown +1 more
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TL;DR: A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data as discussed by the authors, and the preferred embodiment provides a store and forward architecture configured around a switch with prioritization on data pathways critical to high throughput.
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Patent
DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer
Michael J. Bowes,Brian A. Childers +1 more
- 28 Jan 1994
TL;DR: In this article, a direct memory access (DMA) controller is connected with the CPU bus of a computer system through a bus interface and also to an I/O bus, which is connectable to one or more DMA controllers.
57
Patent
High performance multifunction direct memory access (DMA) controller
Jianhua Pang
- 10 Feb 1997
TL;DR: In this article, a direct memory access (DMA) controller with memory-to-memory data transfer capability, a programmable fixed priority scheme, programmable wait state, a buffer chaining mode, a cascade-master mode, separate channels for internal and external devices, and programmable 8 or 16 bit requester bus size.
44
Patent
Computer system having programmable DMA control
Chester Asbury Heath,Jorge Eduardo Lenta +1 more
- 27 Mar 1987
TL;DR: In this paper, a computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access is considered, and each peripheral has a channel priority value.
42
Patent
Direct memory access transfer control circuit
Ryohei Higuchi
- 06 May 2002
TL;DR: In this paper, a transfer waiting time period from the reception of one DMA-transfer request signal to the assignment of the DMA transfer is measured in a transfer wait time counter for each DMA request signal, and the transfer waiting times are stored in a storing circuit and are selectively read out.
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