Digital free-running clock synchronizer

Patent

Digital free-running clock synchronizer

- 17 Nov 1986

9

TL;DR: In this paper, a digital free-running clock oscillator with an asynchronous timing signal from an external source is provided with a protection circuit for preventing a logic race condition in the synchronizing circuit during a period of coincident transition of the oscillator output and the external timing signal.

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Citations

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Tuning circuit for an RC filter

Mark J. Chambers, +2 more

- 01 Jul 1994

TL;DR: In this paper, a tuning circuit (202) uses a precision current reference (Iref) along with an analog-to-digital converter (218) to produce a digital output (228) to represent variations of internal resistance values.

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Built-in self test method for measuring clock to out delays

Robert W. Wells, +2 more

- 14 Jul 1998

TL;DR: In this paper, the authors proposed a test circuit with a feedback path and a free-running oscillator that automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node to establish the period of the oscillator.

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Circuit for measuring signal delays in synchronous memory elements

Christopher H. Kingsley, +3 more

- 22 Jul 1999

TL;DR: In this paper, the authors present a circuit that measures a signal propagation delay through a series of memory cells on a programmable logic device, where each RAM cell is initialized to store a logic zero and the output of the first RAM cell rises to a logic one.

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49

Patent

Built-in self test using pulse generators

Gil A. Speyer, +5 more

- 24 Apr 2002

TL;DR: In this paper, a test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator, and the oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node.

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Method for implementing dynamic burn-in testing using static test signals

Barry Wong

- 23 Jan 2001

TL;DR: In this article, a method for dynamically burn-in testing a PLD by either configuring or fabricating the PLD to implement a self-executing logic operation that automatically and repeatedly turns on and off selected transistors using only static test signals.

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12

References

Patent

Clock system having adaptive synchronization feature

William W. MacGregor

- 12 Jul 1976

TL;DR: In this article, a clock cycle is provided by a delay device, the output of which is coupled via an inverter to the input thereof, which inverter is combined in a gate structure so as to enable such clock cycle and derivative clock pulses coupled to be generated as a signal passes through the delay device.

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54

Patent

Asynchronously controllable successive approximation analog-to-digital converter

Daniel F. Chan, +1 more

- 22 Apr 1983

TL;DR: In this article, a successive approximation analog-to-digital converter controllable by signals to start and interrupt conversion asynchronously with respect to clock signals used to regulate operation of the converter is presented.

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21

Patent

High speed processing restarting apparatus

Steven M. O'Brien

- 28 Jul 1980

TL;DR: In this article, the authors present an apparatus for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal, where the continuous running master clock is employed to generate a plurality of phase related new clock signals.

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21

Patent

Stretch and stall clock

Gary J. Goss, +1 more

- 02 Aug 1976

TL;DR: In this paper, a system clock mechanism which can be either stalled (i.e. held indefinitely in a high state) or stretched, i.e., changed the rate of pulse occurrence, is presented.

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