Data transfer system

TL;DR: In this article, the authors propose to attain data transfer without transmitting/receiving conditional data by accessing a memory from the 1st processor and the 2nd processor having priority lower than that of the first one through a bus line switching part.

Abstract: PURPOSE:To attain data transfer without transmitting/receiving conditional data by accessing a memory from the 1st processor and the 2nd processor having priority lower than that of the 1st one through a bus line switching part. CONSTITUTION:A CPU10 turns an access request signal 23 from the L level to the H level. When a CPU11 turns a holding response signal 14 from the L level to the H level, the bus line switching part 21 operates so as to connect a bus line 25 to a RAM22 and the CPU10 stops its waiting operation, so that the RAM22 can be accessed. At that time, the CPU10 writes data to be transferred to the CPU11 in the RAM22. After completing the writing of the data, the CPU10 turns the access request signal 23 from the H level to the L level. Consequently, the bus line switching part 21 connects the bus line 24 to the RAM22 and the CPU11 reads out data stored in the RAM22.