Data storage system

TL;DR: In this paper, a controller is configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased.

TL;DR: In this paper, the authors define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for at least a first duration of time, and they define a controller operative to reserve for data retention purposes.

TL;DR: In this article, a system for storing a plurality of logical pages in a set of at least one flash device, each flash device including an erase block in the set of erase blocks, is described.

TL;DR: In this paper, a system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundant bytes generated, and the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the storage location.

TL;DR: In this paper, a nonvolatile memory which is configured to include a plurality of word lines disposed in a row direction, bit lines disposing in a column direction perpendicular to the word lines, and a first select gate line connected to each of the gate electrodes of the first select transistors is presented.

TL;DR: In this article, a semiconductor integrated circuit device includes a first data transfer line electrically connected to a first memory cell block, a second data-transfer line connected to the second memory cell, a charge/discharge circuit which charges or discharges a voltage node on the basis of the data held in the third data-store circuit, a first connecting circuit which electrically connects the voltage node to any one of the first and second data transfer lines, a fourth data store circuit, and a second connecting circuit connecting the fourth data-stores circuit to the voltage nodes.

TL;DR: In this paper, a readout counter 13 counts readout count from a nonvolatile memory cell array and outputs a signal to start up refreshing operation when the count is equal to or higher than a preset reference value for comparison.

TL;DR: In this article, a power-on reset function that establishes logic circuits in a memory chip at an initial stable state and a power on read function that triggers a read operation of the memory chip is presented.