Patent
Data processor with individually writable register subword locations
Dale C. Morris
- 30 Sep 2002
8
TL;DR: In this paper, a data processor includes program registers with individual byte-location write enables, which enables a precision pipeline to respond to read requests by accessing a program register or pipeline stage on a byte-by-byte basis.
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Abstract: A data processor includes program registers with individual byte-location write enables. Bypass networks allow a precision pipeline to respond to read requests by accessing a program register or pipeline stage on a byte-by-byte basis. The data processor can thus write to individual byte locations without overwriting other byte locations within the same register. The data processor has an instruction set with instructions that combine two operands and yield a one-byte result that is stored in a specified byte location of a specified result register. Eight instances of this instruction can pack eight results into a single 64-bit result register without additional packing instructions and without using a read port to read the result register before writing to it. As plural functional units can write concurrently to different subwords of the same result register, a system with four functional units can pack eight results into a result register in two instruction cycles.
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Citations
Patent
Indirect indexing instructions
Dale C. Morris
- 17 Sep 2002
TL;DR: In this article, a data processor includes an instruction decoder, an execution unit, a general-purpose register file, and an index-register file, which is used to facilitate table lookups.
4
Patent
Execution method of system register access instruction
Sun Caixia,Wang Yongwen,Dou Qiang,Zhang Chengyi,Gao Jun,Ni Xiaoqiang,Sui Bingcai,Huang Libo,Zheng Zhong,Wang Junhui,Guo Wei,Lei Guoqing +11 more
- 20 Nov 2018
TL;DR: In this paper, an execution method of a system register access instruction is described, which is based on splitting the same operation into two micro-operations and bypassing the result of the SPU to an input data bus of the FU0.
2
Patent
Allocating register halves independently
David P. Belanger,Christopher A. Lapkowski,Chwan-Hang Lee +2 more
- 03 Sep 2010
TL;DR: In this article, the authors propose to use register half-coded instructions to manipulate the register halves independently when performing register allocation during program compilation, thereby doubling the number of registers available for allocation, which in turn may reduce spill code and improve run-time performance.
2
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Patent
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Patent
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