Command encoded delayed clock generator

Patent

Command encoded delayed clock generator

- 29 Apr 1996

19

TL;DR: In this article, a clock feeding circuit to a semiconductor memory is defined, where the memory is comprised of independent control circuits each requiring a clock signal, comprising apparatus for receiving a control signal applied to one of the control circuits, and apparatus for applying the clock signal to the other independent control circuit.

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Citations

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Method and apparatus for processing pipelined memory commands

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- 27 Aug 1998

TL;DR: In this article, a method and apparatus for processing pipelined command packets in a packefized memory device is presented, where the command packets are initially stored in one of several command units, and the commands are subsequently coupled to a common command processor for execution.

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Ian W. Jones, +1 more

- 25 Nov 2002

TL;DR: In this article, a clock distribution system provides N clock phases and, if the phases have an order, there is one jitter source provided between each of the first N−1 phases and the following phase, so that each phase has a jitter relative to each other phase.

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References

Patent

Clock-synchronous semiconductor memory device

Jun Ohtani, +2 more

- 09 Sep 1994

TL;DR: In this article, the data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave register of being in use.

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71

Patent

Semiconductor memory device having extended data out function

Shigeru Mori, +2 more

- 22 Nov 1994

TL;DR: In this article, the output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal, and the output terminals are set to a high impedance state before each output data is provided from the input buffer circuit.

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29

Patent

Semiconductor memory system having a write control circuit responsive to a system clock and/or a test clock for enabling and disabling a read/write latch

David B. Grover, +2 more

- 31 Aug 1994

TL;DR: In this paper, a memory system having a read/write head is provided, where a system clock or a test clock can be used to initiate a pulse for enabling the read or write head during a write period, with a write clock having an input coupled to the system clock also used to terminate the enabling or control pulse during the write period.

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14

Patent

Serial access memory device

James Jing-Yuan Lin

- 29 Apr 1994

TL;DR: In this paper, a serial access memory device with a first data terminal and a memory cell array having a plurality of address locations is described, which can be used with a voice recorder controller.

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12