Patent
Coherent memory scheme for heterogeneous processors
Ian C. Hendry,Rajabali M. Koduri +1 more
- 07 Apr 2011
21
TL;DR: In this paper, the authors present a method for maintaining cache coherence between two or more heterogeneous processors, such that the first and second processing units share at least a portion of the memory and one or both of the first processing units may maintain internal cache-coherence at a first granularity, while maintaining cachecoherence between the first processor and the second processor at a second granularity.
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Abstract: Systems, methods, and devices for maintaining cache coherence between two or more heterogeneous processors are provided. In accordance with one embodiment, such an electronic device may include memory, a first processing unit having a first characteristic memory usage rate, and a second processing unit having a second characteristic memory usage rate lower than the first. The first and second processing units may share at least a portion of the memory and one or both of the first and second processing units may maintain internal cache coherence at a first granularity, while maintaining cache coherence between the first processing unit and the second processing unit at a second granularity. The first granularity may be finer than the second granularity.
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Citations
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