Patent
Array of data processing elements with variable precision interconnect
Paul B. Wood
- 21 Apr 2006
15
TL;DR: In this paper, a variable precision interconnect (VPI) is used for processing data in a row-column array of data processing elements coupled with variable precision data processing interconnects.
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Abstract: Systems and methods for processing data using an array (11) of data processing elements (13) that are coupled together with a variable precision interconnect (14) One embodiment comprises data processing elements coupled by variable precision interconnects to form a row-column array (11) The interconnects (14) and/or data processing elements (13) may be synchronous or asynchronous The data processing elements (13) may operate in a fixed manner, or they may be programmable, and selectable data processing elements (13) in the array may be bypassed The interconnects (14) and data processing elements (13) may be configured to handle data in a digit-serial manner, with tags (25, 26) for each digit identifying whether the digit is the first and/or last digit in a data word The data processing elements may be coupled to a system bus (54, 55) that enables communication of data between the data processing elements and external devices and allows control information to be communicated to and from the data processing elements
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Citations
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References
Patent
Minimal connectivity parallel data processing system
Harry F. Smith
- 14 Nov 1988
TL;DR: In this paper, a control data processor is coupled to each of the cells within a given plane in a manner which provides for simultaneous communication with each cell within the plane, and the status signal may be expressed, when asserted, of a processing state common to all the cells in the plane.
50
Patent
Asynchronous self-tuning clock domains and method for transferring data among domains
Theodore H. Kehl,Steven M. Burns +1 more
- 30 Sep 1994
TL;DR: In this paper, a four-way handshaking method is used to perform inter-domain data transfers by a fourway hand-shaking algorithm, and an interdomain arbiter is implemented at each domain for deciding which domain's request is to be granted during an immediate clock period.
40
Patent
Parallel processor system
Thierry Collette,Josef Kaiser,Renaud Schmit,Hassane Essafi +3 more
- 30 Jul 1992
TL;DR: In this article, a multiprocessor system is described where the processors communicate between each other asynchronously while carrying out synchronous processing, and each processor is associated with a cell connected to its neighbors by a ring network through which circulate messages for the processors.
31
Patent
Systolic array for multidimensional matrix computations
Emdadur R. Khan
- 04 Oct 1990
TL;DR: In this article, a multidimensional systolic array processor uses a multi-dimensional array of systolically coupled processing elements to perform matrix-vector multiplication of matrix and vector signal sets.
22
Asynchronous FIFO Interfaces for GALS On-Chip Switched Networks
Daewook Kim,Manho Kim,Gerald E. Sobelman +2 more
- 01 Oct 2005
TL;DR: A novel design approach that combines the advantages of on-chip switched networks (OCSNs) and the globally asynchronous, locally synchronous (GALS) design methodology using the mechanism of asynchronous FIFO buffers is presented.