Patent
Apparatus, method and computer system for reducing power consumption of a processor or processors upon occurrence of a failure condition affecting the processor or processors
Viktor Andrew Tymchenko
- 10 Sep 2001
33
TL;DR: In this paper, a signal is provided which indicates a failure condition affecting the processor such as an overtemperature condition or a failure or reduction in performance of a cooling mechanism, in response to the signal, a power consumption of the processor is periodically reduced.
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Abstract: An apparatus, a method and a computer system can be used to reduce power consumption of one or more processors in response to a failure condition such as an overtemperature condition affecting the processor or processors. A signal is provided which indicates a failure condition affecting the processor such as an overtemperature condition or a failure or reduction in performance of a cooling mechanism. In response to the signal, a power consumption of the processor is periodically reduced. This can be accomplished by providing a periodic signal to an input of the processor (e.g., a stop clock input or a processor enable input). The processor reduces power consumption by stopping an internal clock of the processor, for example. The periodic signal can be provided to the input of the processor to periodically reduce power consumption. In this manner, power consumption of the processor may be reduced without shutting down the processor entirely, while maintaining some processor functions and without missing the receipt of any signals corresponding to vital functions of the processor system while the power consumption of the processor is reduced.
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Citations
Patent
Automated method and apparatus for processor thermal validation
II James G. Hermerding
- 30 Dec 2002
TL;DR: In this paper, an application program is employed to selectively execute thermal stress code to cause the platform's processor to dissipate an amount of power corresponding to a predetermined value, such as a thermal design power dissipation value specified by the processor's manufacturer.
58
Patent
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Dong Chen,Dozsa Gabor,Mark E. Giampapa,P. Heidelberger +3 more
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54
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TL;DR: In this paper, a system and method for supporting collective communications on a plurality of processors that use different parallel programming paradigms, in one aspect, may comprise a schedule defining one or more tasks in a collective operation, an executor that executes the task, a multisend module to perform the data transfer functions associated with the tasks, and a connection manager that controls one or multiple connections and identifies an available connection.
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TL;DR: In this article, a target core is selected from a plurality of cores based on the effectiveness of the cooling module with regard to each of the plurality of processors, and the selected thread is scheduled for execution by the target core.
45
Patent
Message passing with a limited number of dma byte counters
Michael A. Blocksome,Dong Chen,Mark E. Giampapa,Philip Heidelberger,Sameer Kumar,Jeffrey J. Parker +5 more
- 26 Jun 2007
TL;DR: In this paper, the authors propose a rendezvous protocol for passing messages in a parallel computer system constructed as a plurality of compute nodes interconnected as a network where each compute node includes a DMA engine but includes only a limited number of byte counters for tracking a number of bytes that are sent or received by the DMA, where the byte counters may be used in shared or exclusive counter modes of operation.
31
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Patent
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Patent
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Patent
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Patent
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