A New Algorithm for Floorplan Design
D. F. Wong,C. L. Liu +1 more
- 02 Jul 1986
- pp 101-107
TL;DR: A new algorithm for floorplan design using the method of simulated annealing to carry out the neighborhood search effectively and achieves a simultaneous minimization of area and total interconnection length in the final solution.
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Abstract: We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.
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Citations
A linear programming-based algorithm for floorplanning in VLSI design
Jae-Gon Kim,Yeong-Dae Kim +1 more
TL;DR: This paper focuses on the problem of placing a set of blocks on a chip with the objective of minimizing area of the chip as well as total wire length and uses the sequence-pair suggested by Murata et al. to represent the topology of nonslicing floorplans.
The formal verification of a pipelined double-precision IEEE floating-point multiplier
Mark D. Aagaard,Carl-Johan H. Seger +1 more
- 01 Dec 1995
TL;DR: This paper presents the formal verification of a radix-eight, pipelined, IEEE double-precision floating-point multiplier using a mixture of model-checking and theorem-proving techniques in the Voss hardware verification system.
Annealing placement by thermodynamic combinatorial optimization
TL;DR: This article presents a combinatorial optimization method directly derived from both Thermodynamics and Information Theory, and has been compared with a custom Simulated Annealing tool on a set of benchmark circuits for the FPGA (Field Programmable Gate Arrays) placement problem.
Thermal benefit of multi-core floorplanning: A limits study
Karthik Sankaranarayanan,Brett H. Meyer,Mircea R. Stan,Kevin Skadron +3 more
TL;DR: This paper evaluates techniques from the literature, including manipulating core orientation, L2 cache bank insertion, and hierarchical floorplanning, and introduces two new techniques, core mingling and core scattering, in order to bound the potential benefits of temperature-awarefloorplanning.
References
Optimization by Simulated Annealing
TL;DR: There is a deep and useful connection between statistical mechanics and multivariate or combinatorial optimization (finding the minimum of a given function depending on many parameters), and a detailed analogy with annealing in solids provides a framework for optimization of very large and complex systems.
46.9K
•Book
The Design and Analysis of Computer Algorithms
Alfred V. Aho,John E. Hopcroft +1 more
- 01 Jan 1974
TL;DR: This text introduces the basic data structures and programming techniques often used in efficient algorithms, and covers use of lists, push-down stacks, queues, trees, and graphs.
10.6K
•Proceedings Article
The Timber Wolf Placement and Routing Package
C. Sechen
- 01 Jan 1984
TL;DR: TimberWolf as discussed by the authors is an integrated set of placement and routing optimization programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing.
495
Automatic Floorplan Design
Ralph H. J. M. Otten
- 01 Jan 1982
TL;DR: The problem of allocating area to modules at the highest level of a top-down decomposition is treated and a theorem of Schoenberg is applied to obtain a good embedding of the module space into the plane.
351
A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation
Ulrich Lauther
- 25 Jun 1979
TL;DR: A new placement algorithm for general cell assemblies is presented which combines the ideas of polar graph representation and min-cut placement and the various methods for placement improvement and global routing.
194