Proceedings Article10.1109/DATE.2011.5763085
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
Abbas Rahimi,Igor Loi,Mohammad Reza Kakoee,Luca Benini +3 more
- 14 Mar 2011
- pp 1-6
TL;DR: A parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor clusters is designed.
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Abstract: Shared L1 memory is an interesting architectural option for building tightly-coupled multi-core processor clusters. We designed a parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor clusters. Our interconnect IP is described in synthesizable RTL and it is coupled with a design automation strategy mixing advanced synthesis and physical optimization to achieve optimal delay, power, area (DPA) under a wide range of design constraints. We explore DPA for a large set of network configurations in 65nm technology. Post placementr when the number of both processors and memories is increased by a factor of 4, the delay increases almost logarithmically, to 84FO4, confirming scalability across a significant range of configurations. DPA tradeoff flexibility is also promising: in comparison to the maxperformance 16×32 configuration, there is potential to save power and area by 45% and 12 % respectively, at the expense of 30% performance degradation.
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Citations
•Book
IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society
Ieee Circuits
- 01 Jan 1982
TL;DR: Manuscripts focusing on methods, algorithms, and human-machine interfaces for physical and logical design of integrated-circuit and systems designs of all complexities and practical applications of aids resulting in producible analog, digital, optical, or microwave integrated circuits are emphasized.
730
T-crest
Martin Schoeberl,Sahar Abbaspour,Benny Akesson,Neil Audsley,Raffaele Capasso,Jamie Garside,Kees Goossens,Sven Goossens,Scott Hansen,Reinhold Heckmann,Stefan Hepp,Benedikt Huber,Alexander Jordan,Evangelia Kasapaki,Jens Knoop,Yonghui Li,Daniel Prokesch,Wolfgang Puffitsch,Peter Puschner,Andre Rocha,Claudio Silva,Jens Sparsø,Alessandro Tocchi +22 more
- 01 Oct 2015
TL;DR: Within the T-CREST project the authors propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time.
A 64mW DNN-based Visual Navigation Engine for Autonomous Nano-Drones
Daniele Palossi,Antonio Loquercio,Francesco Conti,Eric Flamand,Davide Scaramuzza,Luca Benini +5 more
TL;DR: In this paper, the authors present the first demonstration of a navigation engine for autonomous nano-drones capable of closed-loop end-to-end DNN-based visual navigation.
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs
Alessio Burrello,Angelo Garofalo,Nazareno Bruschi,Giuseppe Tagliavini,Davide Rossi,Francesco Conti +5 more
TL;DR: This work proposes DORY (Deployment Oriented to memoRY) – an automatic tool to deploy DNNs on low cost MCUs with typically less than 1MB of on-chip SRAM memory and releases all the developments – the DORY framework, the optimized backend kernels, and the related heuristics – as open-source software.
148
A 64-mW DNN-Based Visual Navigation Engine for Autonomous Nano-Drones
Daniele Palossi,Antonio Loquercio,Francesco Conti,Eric Flamand,Davide Scaramuzza,Luca Benini +5 more
TL;DR: In this article, a navigation engine for autonomous nano-drones capable of closed-loop end-to-end DNN-based visual navigation is presented, which is based on GAP8, a novel parallel ultralow power computing platform, and a 27g commercial, open-source Crazyflie 2.0 nano-quadrotor.
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