Abstract: AlGaN/GaN High Electron Mobility Transistor (HEMT) frequently employs field plate techniques to improve the device's reliability and optimum performance. This literature review investigates the effects of field plate-engineered GaN-based High Electron Mobility Transistors (HEMTs) on RF applications, specifically focusing on elevated breakdown and cut-off frequency. The study comprehensively examines various field plate designs employed in HEMTs, highlighting their significant contributions. The research explores three primary and six secondary types of field plates, each operating on distinct principles to enhance device parameters. For instance, gate, drain, and source-type field plates in GaN-based HEMTs can imprcove breakdown, power and output resistance. These field plate techniques influence device stability, specific resistance and ensure uniform electron flow across terminals. Moreover, the implementation of a drain field plate improves power application performance by reducing the impact ionization rate. The utilization of field plate techniques in GaN-based High Electron Mobility Transistors (HEMTs) offers several benefits, including the minimization of parasitic effects and the reduction of the source-to-gate region without significantly impacting the device's breakdown voltage.

Abstract: Physical unclonable function (PUF) is a hardware security primitive with significant application potential. However, strong PUF is vulnerable to machine learning attacks based on modeling attacks. Although various resistance techniques have been proposed, strong PUF suffers from deficiencies in its resistance to machine learning attacks, hardware overhead, and reliability. This study proposes a highly reliable and secure lightweight PUF that complicates the original challenge using an internal response. Specifically, the internal response is used to determine the odd/even bit flip or left/right cyclic shift of the original challenge to achieve preliminary obfuscation, and byte substitution that exploits an S-box is performed on the preliminary obfuscated challenge to achieve deep nonlinear obfuscation. Experimental results on a Xilinx Artix-7 FPGA show that the proposed PUF is not only highly resistant to machine learning (ML) attacks but also has a low hardware overhead. An arbiter PUF(APUF), which uses the proposed obfuscated scheme with a 64-bit challenge length, was evaluated by three advanced machine learning algorithms with up to 600,000 challenge–response-pairs (CRPs) in the dataset, and the observed prediction accuracy was less than 56 %. Moreover, the PUF is unique, reliable, and has a significantly lower hardware overhead than other prior anti-attack PUFs.

Abstract: In this work, a self-powered synchronous magnetic flux extraction (SP-SMFE) circuit is proposed for electromagnetic energy harvesting. It's a bridgeless direct ac-dc converter, that uses a large-value external inductor L to store and transfer energy. By comparing the voltage across L, SP-SMFE achieves the peak detection of the inductor current Iem without an external power supply and transfers the energy to the load when Iem reaches the peak value, which can maximize the energy extraction from the electromagnetic transducer. Simulation results show that the output power of SP-SMFE is much higher than that of the voltage doubler circuit under the load range of 1–100 kΩ and the frequency range of 20–140 Hz. The input ac voltage with 4 V amplitude is rectified and stepped up to 59 V dc by SP-SMFE at the load of 100 kΩ and the frequency of 40 Hz. Experiment results verify the effectiveness of the SP-SMFE circuit in power harvesting at low frequencies and large loads.

Abstract: This manuscript presents the analytical model of a novel biosensor called Graded JAM Split Gate-All-Around (GJAM-SGAA) Bio-FET for the detection of Avian Influenza antibody and DNA. The GJAM-SGAA Bio-FET utilizes a silicon Gate-All-Around FET which operates in the Junctionless Accumulation Mode (JAM), with a graded doping in the channel. This Bio-FET also features a gate underlap double sided cavity that enables detection of biomolecules without the use of labels. Gate underlap cavities overcome the fabrication complexity of nanocavities and provides structural stability. A comparative analysis between the GJAM-SGAA Bio-FET and non-graded JAM Split Gate-All-Around FET (SGAA-FET) demonstrates that the proposed BioFET has 5.72 times higher ION current sensitivity, 5.3 times increase in threshold voltage sensitivity (SVth), and 2.13 × 102 times improvement in switching ratio sensitivity for avian influenza biomolecule. The SVth of proposed biosensor is compared with the existing biosensors and found that a triple-metal engineered gate and graded doped channel substantially boosts the sensitivity of proposed biosensor.

Abstract: This study investigates how incorporating a dual-k spacer (SiO2 + HfO2) affects the RFIC design feasibility of a junctionless-accumulation-mode (JAM) stacked-gate (GS) gate-all-around (GAA) FinFET in the sub-10 nm range. The proposed device is compared with a conventional FinFET and those without a spacer, air, and a single-k spacer (SiO2). At a low voltage power supply, fringing field effects raise the proposed device's on-current by 35.34% and reduce the off-current by more than 76 times compared to conventional FinFET, thereby improving electron velocity, energy band profiles, transconductance, device efficiency, etc. Thus, the proposed device is well-suited for high-performance CMOS circuits. Further investigation shows that integrating a dual-k spacer reduces the output conductance, which boosts the intrinsic gain and early voltage by five times the value recorded for conventional FinFET. Although the cut-off frequency drops by 15.98%, the GTFP and GFP soar by 475.67% and 352.25%, respectively. Consequently, JAM-GS-GAA FinFET with dual-k spacer is an encouraging device for low-power RFIC circuits.

Abstract: This manuscript for the first time integrates the traditional FinFET architecture involving Bottom spacer (BS), Tapering, and Junctionless (JL) concepts to investigate the device analog/RF performance at sub- 5 nm technology node. Initially, to come up with an optimal BS and Fin angle (θ), a variation in these values is performed and found that higher θ and lower HBS would be the best fit to optimize the device performance. Following this, a variation in gate length (Lg) is rendered amidst 8 nm–14 nm and noticed that least Lg would be preferable for some parameters sacrificing other parameters which depends upon the application requirement. Later, at fixed Lg, fin angle (θ) variations (80°–87°) are performed to observe the analog/RF performance and noticed that higher θ fetched better performance. Further, at this optimal Lg and θ, height of the Bottom spacer (HBS) is varied between 5 nm–25 nm to inspect the device characteristics and least HBS must be preferred. At last, the dielectric material of BS is changed (SiO2, Si3N4, HfO2) to observe if the material is showing any impact on the device and noticed that replacement of lower dielectric materials with higher dielectric materials is not a bad idea and delivers excellent performance by optimally choosing dielectric values. Further the CMOS inverter performance is also examined. The flow of this manuscript is arranged in such a way that it provides a complete flavour to the design engineers in choosing the best electrical/analog/RF and circuit performance of JL - BS - Tapered FinFET.

Abstract: In this paper, a novel Dual-Source Elevated-Channel Dopingless TFET (DSEC-DLTFET) is proposed to enhance the dc and analog/high-frequency (HF) performance of the device. TCAD-based simulation results reveal that an additional source region of the proposed device improves the ON-state current by enhancing the rate of charge carriers tunneling into the channel during ON-state while the elevated channel induces a barrier for the charge carriers tunneling during OFF-state, thereby reducing the leakage current in the device. The improvement in the ON- and OFF-state currents is found to be an order of ∼2 and ∼3 as compared with the conventional DLTFET. Furthermore, to eliminate the trade-off between the ambipolarity and ON-state current, drain metal engineering (DE) is employed to the proposed device where in the drain metal, which is mainly responsible for the creation of electron plasma in the drain region, is composed of two different work functions. The higher work function metal near to the channel-drain interface enhances the barrier width, thus restricting the tunneling rate of charge carriers during the negative gate bias i.e. ambipolar state. Moreover, DE-DSEC shows the improvement in HF performances owing to reduction in the parasitic capacitances. Due to the improved DC and analog/HF performances, transient response of DE-DSEC based n-TFET inverter is also found to be better than that of the conventional DLTFET.

Abstract: An automated sizing approach for analog circuits using evolutionary algorithms is presented in this paper. A targeted search of the search space has been implemented using a particle generation function and a repair-bounds function that has resulted in faster convergence to the optimal solution. The algorithms are tuned and modified to converge to a better optimal solution with less standard deviation for multiple runs compared to standard versions. Modified versions of the artificial bee colony optimisation algorithm, genetic algorithm, grey wolf optimisation algorithm, and particle swarm optimisation algorithm are tested and compared for the optimal sizing of two operational amplifier topologies. An extensive performance evaluation of all the modified algorithms showed that the modifications have resulted in consistent performance with improved convergence for all the algorithms. The implementation of parallel computation in the algorithms has reduced run time. Among the considered algorithms, the modified artificial bee colony optimisation algorithm gave the most optimal solution with consistent results across multiple runs.

Abstract: Physically Unclonable Functions (PUFs) are becoming more widely recognized as tamper-resistant, high-entropy hardware security primitives. Leveraging the intrinsic manufacturing properties of integrated circuits, PUFs provide a lightweight, cost-effective technique for device identification and cryptographic key generation. Despite the existence of various PUF designs and architectures, the ring oscillator (RO) PUF stands out as one of the most notable. This significance is due to its simplicity of implementation and outstanding performance metrics. However, traditional RO-PUFs are often classified as weak PUFs because they support a limited size of input-output combinations. This paper introduces a configurable inversion unit designed to construct a lightweight, robust architecture configurable (RAC) RO-PUF. The proposed unit comprises an XOR gate, an XNOR gate, and a multiplexer. The RACRO-PUF significantly increases the size of generated output bits while efficiently utilizing minimal hardware resources. The performance of the RACRO-PUF stands out in evaluations, recording a uniqueness of 49.78 %, uniformity of 49.42 %, reliability of 97.72 %, and impressive randomness of 98.34 %.

Abstract: The current collapse and hot electron effect of 100 V normally-off GaN power HEMTs are investigated. The 100 V GaN-on-Si power HEMTs are fabricated on an industrial 200 mm Si CMOS compatible technology platform. The double pulse test (DPT) and the dynamic high temperature operating life (DHTOL) test are implemented to verify the dynamic on-resistance (dynamic Ron) stability. Wafer level hot electron reliability test is performed to investigate the effect of high electric field and high current on GaN power HEMT. It is proved that the dynamic Ron stability of 100 V GaN power HEMT is qualified (Ron/Rini, static < 1.2) when the drain-source off-state voltage (Vdsoff) is less than 80 V. It is shown that the dynamic Ron degradation of GaN device is recoverable by means of annealing. Hot electrons reliability is dominated by the high electric field at drain edge and the high current which is source injected electrons flowing to the drain. It is demonstrated that the Vth drift and Ron degradation are extraordinary serious under semi on-state stress condition with Vdsoff = 60 V.

Abstract: In this paper, a high efficiency and high power 165–180 GHz balanced doubler based on the planar Schottky diode is presented. To maximize the efficiency of the doubler in the target frequency band, an in-band embedded impedance optimization method (IEIOM) is adopted. The method aims to extract the conjugate value of embedded impedances of the three-dimensional electromagnetic (3D-EM) model of the diode. Compared to the method of impedance optimization at a single frequency point using Load-Pull, the proposed method not only takes account for both conversion efficiency and bandwidth but also simplifies operation process. To verify the proposed concept, the doubler was fabricated and measured, which exhibits a conversion efficiency of 13%–46% at the 165–180 GHz band under 160–200 mW input power and a 90.88 mW peak output power with a 46% efficiency was measured at 178 GHz when the input power is 198 mW.

Abstract: This work demonstrates a laterally excited shear bulk acoustic wave resonator (XBAR) based on a 300-nm-thick ZY-cut Lithium Niobate thin film, which takes advantages of high frequency, large electromechanical coupling coefficient (kt2) and high quality factor (Q). A bi-electrode structure was proposed to weaken the effects of mechanical and electrical loading introduced by the metal electrodes, while enhancing the coupling between the electric field and stress. In addition, the electrode configurations including interdigitated electrodes (IDEs) number, metal coverage and effective electrode length were studied to eliminate spurious modes and improve resonators' performance. The fabricated devices can achieve the resonant frequency of 5.89 GHz using the first-asymmetric (A1) mode Lamb wave in suspended LiNbO3 thin film. Combined with the high operating frequency and high kt2 characteristics of the A1 mode Lamb wave, the measured results show that the designed bi-electrode structure XBAR achieves a kt2 value of 14 % and a high Q value of 300.

Abstract: In this paper, we propose a graphene RF MEMS switch design for the X–V band. The structural parameters of graphene, such as the number of layers, the thickness of the medium and the material of the upper electrode, were analyzed by HFSS simulation software. The drive voltage of the switch was found to be as low as 3 V. The switching time is 320 ns. The highest isolation is −47.46 dB@8 GHz; In the 2–56 GHz band, the isolation is better than −20dB. Moreover, we carry out the process design of the switch, including key techniques such as graphene beam fabrication and graphene transfer, it shows that the switch has a great application prospect in the future.

Abstract: A detailed analysis of a novel multi-source T-shaped gate Tunnel FET (MS-TTFET) is presented in this study in order to address the main issues with conventional TFETs. Due to its exceptionally low off-state current (IOFF) and remarkable sub-threshold properties, the tunnel field effect transistor has received a great deal of interest for low standby power applications. The MSR's integration into the SOI platform increases the device's on current, which increases the effective tunnelling area in the middle of the source-channel junctions. An isolator oxide has been added to prevent the source and drain regions from being directly coupled. A SiGe pocket has been suggested at the source and channel junction; silicon-germanium, a low bandgap material which enhances the tunnelling of charge carriers. A T-shaped gate can increase the effectiveness of the tunnel junction in order to limit the lower value of the leakage current. The multi-source regions of the T-shaped gate tunnel field effect transistor can boost the on-state current (ION) by improving tunnel junction areas. The device's ION/IOFF ratio, which is 1013 for our suggested construction, is the standard measure of merit for any device. It is possible to achieve an increased ON current of the order of 10−5 A/μm with a negligible subthreshold swing (SS) of 42 mV/decade. Moreover, the effect of low frequency flicker noise on the device behavior has been investigated.

Abstract: This paper presents a novel multi-step single slope analog to digital converter (MS SS ADC). The proposed ADC splits the 12-bit conversion into 3 steps, including 1-bit half section decision, 4-bit coarse conversion, and finally 8-bit fine conversion with 1-bit redundancy. The conversion step is substantially reduced from conventional 4096 to 276. The linearity of the ADC is guaranteed by a stable common mode voltage of the comparator varying only within 31.25 mV. Moreover, two high-accuracy ramp calibration techniques are utilized to correct the current variation in the fine ramp and the slope error between the coarse and fine ramps. A hybrid comparator is utilized in the ADC to save power while maintaining the performance. The ADC is designed and simulated in 0.18 μm CMOS process with 7.5 μm width. The differential nonlinearity and integral nonlinearity of the proposed ADC are reduced from +0.3/-1 LSB and +3.1/-2.55 LSB to +0.3/-0.3 LSB and +1/-0.45 LSB at 61.7 kS/s sample rate by the calibrations.

Abstract: This paper reports the sensitivity analysis of double gate TFET using the Transition Metal Di chalcogenide (TMD) material in photo sensitive region with the help of technology computer aided design (TCAD) simulator tool. The sensitivity analysis elaborates the significance of TMD material for optical applications. The photo sensitivity analysis is exhibited for the variation in wavelength (λ) of incident light under the visible range of spectrum. Furthermore, we have executed the performance of photo sensor by varying the position of illumination window. Result reveals that sensitivity, responsivity, and quantum efficiency of sensor are improved at λ = 320 nm. The maximum value of signal to noise ratio (SNR) and responsivity (R) are 63.2 dB and 106, respectively, under the visible range. This TMD material based TFET photo-sensor will be useful for the next generation low power highly sensitive optical devices.

Abstract: The quest for optimal VLSI Floorplanning (FP) addressing noteworthy challenges namely Area, Wirelength, and Temperature remains an ongoing field of research. Prevailing FP designs individually optimize these constraints that increase the model complexity with reduced efficiency. Given this motivation, this study provides an optimum FP aimed at minimizing the overall chip area by adhering to the standard design requirements. Accordingly, the divide-and-conquer model of Dynamic Programming (DP) adopted in this work simultaneously optimizes the chip area by devising separate analytical cost functions related to the physical design parameters that are then collated to yield the compact Floor plan. The formulated DP optimization coined as Weighted Aggregated DP-Based FP (WADPFP) adaptively tunes the cost function using rank-sum scaled weights and the discount factor thereby reducing congestion and hotspots. This objective is met using two novel recursive functions ensuring temperature and area scalability. Simulation and synthesis of the proposed FP on the Microelectronic Centre of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC) Benchmark circuits demonstrated the viability of the automated FP design by registering 6.05%, 13%, and 4.35% reduction in area, wirelength, and temperature respectively in comparison with the traditional and recent peers. Additional analysis on the AMI49_X benchmark circuits emphasizes the scalable nature of the introduced WADPFP.

Abstract: A fully-integrated 2.9 MHz RC relaxation oscillator is presented in this paper. In order to eliminate performance degradation caused by propagation delay at low power, the delay equivalent electric charges technique based on comparator offset cancellation structure is utilized. The oscillator is designed in 180 nm CMOS process and 1-point trimmed to operate within 0.2% precision by a specific mathematical model. With core area of 0.115mm2, the oscillator achieves a frequency stability of 45 ppm/°C in range from −40∼+125 °C and demonstrates an energy efficiency of 2.49 μW/MHz.

Abstract: To solve the bottleneck of amplitude and phase accuracy deterioration caused by process and unpredictable errors, this paper proposes a Ku-band common-leg transceiver with built-in configurable register to achieve 64-state amplitude and phase accuracy correction, respectively, by redefining control codes of each state after taping out. Two-stage cascaded variable gain amplifiers (VGAs) and the vector-summing phase shifter (VSPS) with tail current source controlled by DAC are adopted to achieve large amplitude and phase coverage of 31.5 dB with the LSB of 0.5 dB and 360° with the LSB of 5.625°, respectively. According to the measurement results, in the frequency range of 14–18 GHz, the chip has amplitude accuracy with the root mean square (rms) error of ＜ 0.4 dB, while the rms phase error is ＜ 5.3°. The phase shifting accuracy is measured to be ＜ 2.2°, while the rms amplitude error is ＜ 0.67 dB. The receiving and transmitting channels have reference gain of 3.6–6 dB and 8–10.4 dB, respectively. The whole transceiver occupies 3 × 2.3 mm2 chip area including pads.

Abstract: An easy-to-use efficient auto-design approach to achieve a synchronous optimization and solution for multiple performance objectives of a CMOS low-dropout regulator (LDO) circuit is proposed. As a core algorithm, response surface methodology (RSM) is adopted to automatically implement the design parameter modeling and solving of the LDO. The precision response surface models for the temperature coefficient (TC) and power supply rejection ratio (PSRR) are established efficiently based on only 27 sets of Cadence sampling datasets, by which the optimal performance solution with a superior tradeoff on TC and PSRR can be obtained. Along with a complete auto-design flow, the pre/post-layout simulations of the LDO circuit by SMIC 180 nm/3.3 V CMOS technology are performed, it can be observed that the auto-improved LDO has a significant better 35.20 ppm/°C TC feature compared with 48.46 ppm/°C that recorded by the manual design. Synchronously, the PSRR is improved from −59.497 Hz@DC to −92.89 Hz@DC with a great increase ratio by 56 % up.

Abstract: This paper presents a power amplifier (PA) based on the mismatch-consistent magnetically coupled resonator (MCR) technique, which employs adjustable dual-pole to achieve a wide operating frequency range. The in-band no gain ripple condition of the proposed mismatch-consistent MCR is systematically analyzed and derived. By applying this condition to the mismatch-consistent MCR technique, the in-band gain flatness in broadband is improved. An ultra-wide wiring method for the power-combining structure is proposed to further improve the in-band gain flatness by reducing parasitic effects. Meanwhile, an active broadband matching network without any on-chip inductor is used to obtain a -11 dB input return loss (S11) across the whole bandwidth. Implemented in 40-nm CMOS process, the proposed PA achieves a saturated output power of 19.2 dBm, an output 1 dB compression point of 17.8 dBm, a peak power added efficiency of 29.7 %, and only 0.5 dB in-band gain ripple at 8.2-16.2 GHz. The amplifier achieves a 3 dB bandwidth from 6 to 18 GHz while the fractional bandwidth reaches 100 %, realizing wideband and flat frequency response.

Abstract: This article proposes investigation of low power performance of a fin field-effect transistor (FinFET) with surrounding gates through a calibrated technology computer-aided design (TCAD) framework. The proposed silicon body FinFET has a dual core structure in its source and drain regions, which offers opportunities for tuning its performance in terms on current, off current, threshold voltage and sub-threshold swing. Through variation of height and width of inner and outer cores, different electrical parameters are reported. To assess the impact of corner effect on device performance, gate edge suppression is introduced from all four sides, and their effects are reported for two cases: one, with equal suppressions, and the other, with suppressions in a 2:1 ratio. The percentage of occupancy of the inner core with respect to the overall volume of the source/drain decides the electrical parameters for different cases of core dimensions. For a 35 % reduction in the channel length, the overall low power performance of the device improves.

Abstract: A shallow-trenched Lateral Double-Diffused MOSFET with folded drift region (FD LDMOS) is proposed in this paper. The new structure divides the drift region into two parts. The left side is introduced in a shallow trench, and the right side is used to take advantage of the buried oxide bump layer. The new structure optimizes the lateral and vertical electric fields simultaneously. The self-adaptation of the drift region improves the doping concentration (Ndd), reducing specific on-resistance (Ron,sp) and parasitic capacitance. The simulation results show that compared with the conventional LDMOS (Con. LDMOS), the breakdown voltage (BV) has increased by 53%, and the figure of merit (FOM) has increased by 173.4%; the power-added efficiency (PAE) near the P3dB operating point is increased from 44.43% to 63.67% at the frequency of 1.2 GHz.

Abstract: —In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field effect transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of the SHE and is dependent on the gate/drain voltage in different devices. Furthermore, the lattice maximum temperature-rise (ΔTmax), which directly leads to current degradation due to stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased gate/drain voltages. The ΔTmax increases at a decreasing rate with increasing VGS but increases approximately linearly as VDS increases. To investigate the origin of these behaviors, changes in thermal resistance (Rth) due to the shift in hot spot location and the redistribution of heat source under different applied voltages are also examined. The Rth decreases as VGS increases and slightly increases at a larger VDS. The Rth of NSFETs is generally larger than that of FinFETs, and the narrow-width NSFET (N-NSFET) has the largest Rth owing to the GAA structure and narrower sub-fin structure. Additionally, the heat flux ratio of the source thermal contact in N-NSFETs is smaller than that in FinFETs for different gate and sub-fin structures, resulting in reduced mean ΔT (ΔTmean) of N-NSFETs under a larger VGS, and therefore, leading to less current degradation. The study provides one effective design guide for GAA NSFETs optimizing their thermal characteristics in advanced nodes.

Abstract: A current-mode two-stage continuous-time pipelined (CTP) ADC for wideband receivers is proposed in this paper, to eliminate power-hungry front-end trans-impedance amplifier (TIA). An improved current mirror with low input impedance and high linearity is used to receive the current input signal and duplicate it to the delay chain and the quantization path of the 3-bit first stage. Then, the residue current is amplified and filtered by an embedded 1st-order TIA and further quantized by the second stage, which is implemented by a VCO-based quantizer to improve ADC energy efficiency and anti-aliasing filtering. Simulation results in a 12 nm FinFET process show that clocked at 4.8 GS/s, the proposed ADC achieves 55.7 dB SNDR for a 600 MHz bandwidth and consumes only 83.4 mW power under supplies of 0.9 V, 1.2 V, and 1.5 V, corresponding to an excellent FoM of 154.3 dB.