VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

System-on-a-chip verification~methodology and techniques

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.

/pdf/survey-of-scan-chain-diagnosis-4ozoy9kont.pdf

Survey of Scan Chain Diagnosis

A method and apparatus for debug, diagnosis, and/or yield improvement of a scan-based integrated circuit where scan chains embedded in a scan core 303 have no external access, such as the case when they are surrounded by pattern generators 302 and pattern compactors 305, using a DFT (design-for-test) technology such as Logic BIST (built-in self-test) or Compressed Scan. This invention includes an output-mask controller 301 and an output-mask network 304 to allow designers to mask off selected scan cells 311 from being compacted in a selected pattern compactor 305. This invention also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations. Computer-aided design (CAD) methods are then proposed to automatically synthesize the output-mask controller 301, output-mask network 304, input chain-mask controller and input-mask network, and to further generate test patterns according to the synthesized scan-based integrated circuit.

Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits

In this paper we address the scan chain diagnosis problem. We propose a new diagnosis flow based on the concept of signal profiling to accurately pinpoint the location of a faulty flip-flop in a scan chain. As compared to the conventional cause-effect or effect-cause analysis, this approach is much more computationally efficient because it does not have to simulate the behaviors of a large number of fault candidates. Also, it is general and applicable to all kinds of faults because it does not assume any specific fault model. Experimental results indicate that this approach can instantly catch a fault within a scan chain quite accurately in most cases.

Quick scan chain diagnosis using signal profiling

Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed a s well. Unlike the previous scan chain diagnosis methods that targeted p ermanent faults only, the proposed method targets both permanent faults and intermittent faults. Three ideas are presented in this paper. First an enhanced upper bound on the location o f candidate faulty scan cells is obtained. Second a n ew method to determine a lower bound is proposed. Finally a statistical diagnosis algorithm is proposed to calculate the probabilities of t he bounded set of candidate faulty scan cells. The proposed algorithm is shown to be efficient and effective for large industrial designs with multiple faulty scan chains.

Statistical diagnosis for intermittent scan chain hold-time fault

When VLSI design and process enter the stage of ultra deep submicron (UDSM), process variations, signal integrity (SI) and design integrity (DI) issues can no longer be ignored These factors introduce some new problems in VLSI design, test and diagnosis, which increase lime-to-market, time-to-volume and cost for silicon debug Intermittent scan chain hold-time fault is one of such problems we encountered in practice The fault sites have to be located to speedup silicon debug and improve yield Recent study of the problem proposed a statistical algorithm to diagnose the faulty scan chains if only one fault per chain Based on the previous work, in this paper, an efficient diagnosis algorithm is proposed to diagnose faulty scan chains with multiple faults per chain The presented experimental results on industrial designs show that the proposed algorithm achieves good diagnosis resolution in reasonable time

Efficient diagnosis for multiple intermittent scan chain hold-time faults

A new algorithm to diagnose intermittent scan chain fault in scan-based designs is proposed in this paper. An intermittent scan chain fault sometimes is triggered and sometimes is not triggered during scan chain shifting, which makes it very difficult to locate the fault sites. In this paper, we provide answers to three questions: (1) Why intermittent scan chain faults happen? (2) Why diagnosis of this type of faults is necessary? (3) How to diagnose this type of faults? The experimental results presented demonstrate that the proposed diagnosis algorithm is effective for large industrial designs with multiple intermittent scan chain faults.

Intermittent scan chain fault diagnosis based on signal probability analysis

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Statistical diagnosis for intermittent scan chain hold-time fault

Efficient diagnosis for multiple intermittent scan chain hold-time faults

Intermittent scan chain fault diagnosis based on signal probability analysis