William M. Johnson
Advanced Micro Devices
57 Papers
1.9K Citations
William M. Johnson is an academic researcher from Advanced Micro Devices. The author has contributed to research in topics: Cache & System bus. The author has an hindex of 25, co-authored 57 publications.
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Papers
Patent
System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
William M. Johnson
- 06 Jun 1989
TL;DR: In this article, a super-scaler processor with branch-prediction information is described, where each instruction cache block stored in the instruction cache memory includes branch prediction information fields in addition to instruction fields, which indicate the address of the instruction block's successor and information indicating the location of a branch instruction within an instruction block.
254
Patent
High performance superscalar microprocessor including a common reorder buffer and common register file for both integer and floating point operations
David B. Witt,William M. Johnson +1 more
- 10 Jul 1995
TL;DR: In this article, the superscalar microprocessor is presented, which includes an integer functional unit and a floating-point functional unit that share a high performance main data processing bus.
195
Patent
Multiple instruction decoder for minimizing register port requirements
William M. Johnson
- 06 Jun 1989
TL;DR: In this article, a multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logical instructions include N register-operand identifiers; arbitration logic coupled to the input latch, for arbitrating read port contentions by the N register operators for M available read ports (where M is less than N).
188
Patent
Streamlined instruction processor
Gigy Baror,Brian Case,Rod Fleck,Philip M. Freidin,Smeeta Gupta,William M. Johnson,Cheng-Gang Kong,Ole Moller,Timothy Alan Olson,David I. Sorensen +9 more
- 03 Mar 1988
TL;DR: In this article, a streamlined instruction processor is proposed to process data in response to a program composed of prespecified instructions in pipeline cycles, which includes an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions from the instruction memory.
105
Patent
Direct memory access apparatus and methods for transferring data between buses having different performance characteristics
William M. Johnson,Timothy Alan Olson,Doruu Jiyon Daton,Sherman Lee,David W. Stoenner +4 more
- 15 Dec 1987
TL;DR: In this paper, direct memory access (DMA) is used to transfer data between a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").
103