The Fast Fourier Transform and Inverse Fast Fourier Transform (FFT/IFFT) are the most significant digital signal processing (DSP) techniques used in Orthogonal Frequency Division Multiplexing (OFDM)-based applications which include day-to-day wired/wireless communications, broadband access, and information sharing. The advancements in telecommunication technologies require an efficient FFT/IFFT processing device to meet the necessary specifications which depend on the particular application. A real-time implementation of high-speed FFT/IFFT processor with less area that operates in minimal power consumption is essential in designing an OFDM integrated chip. A comparative study of efficient algorithms and architectures for FFT chip design is presented in this paper. It is also recommended that mixed-radix/higher-radix algorithm combined with Single-path Delay Commutator (SDC) architecture is appropriate for massive MIMO in 5G, optical OFDM, cooperative MIMO and multi-user MIMO-based applications.

A Survey on FFT/IFFT Processors for Next Generation Telecommunication Systems

Marine Debris is human-created waste dumped into the sea or ocean. It pollutes the aquatic environment and hence very dangerous for ocean species. Removal of marine debris from ocean is necessary to eliminate pollution and to secure aquatic life. A robust and automatic system is essential that detects unnecessary litter of plastic and other garbage at real-time. In this study, we have proposed deep learning based architecture for the detection and classification of marine debris. Histogram Equalization technique combined with Median Filter is used to enhance the contrast of images and to remove noise. Experiments are performed on challenging Forward Looking Sonar Image (FLS) Marine Debris Dataset. This dataset includes ten different types of Debris. The proposed system not only detect the Debris, but also classify it into ten classes. To overcome the challenge of data scarcity, Faster-RCNN with transfer learning of ResNet-50 architecture is used. Faster-RCNN is one of the popular object detection architecture that uses Regional Proposal Network (RPN) and detector at the same time. The proposed methodology significantly improves the state-of-the-art results. Result assessment of our proposed technique achieved recall of (96%) and Mean Overlap bounding boxes of (3.78). Visual and qualitative assessment of proposed methodology shows the effectiveness of presented technique. 

Target Classification of Marine Debris Using Deep Learning

Iterative Error Correction: References

Starting from a discrete density evolution scheme originally introduced by Brian M. Kurkoski et al. which we improved by applying the Information Bottleneck method, we recently presented results on message passing decoders for Low Density Parity Check codes that have much lower complexity than state of the art decoders. In the decoders all node operations are replaced by discrete message mappings of unsigned integers what yields a great complexity reduction. Anyway the decoders perform very close to belief propagation decoding. New included simulation results prove that using a 4 bit integer architecture these decoders loose only 0.1 dB over Eb/No in comparison to an exact belief propagation decoder applied to the quantized output of a Gaussian channel. The most important contribution of this paper is the derivation of the message mapping decoders from the sum-product algorithm. Until now these decoders are assumed to not be linked to this algorithm. In order to reveal the hidden connection, we explain the decoding principle of the message mapping decoders in general factor graphs.

Optimum message mapping LDPC decoders derived from the sum-product algorithm

Video coding is one of the most demanding applications, in terms of computational cost, for portable multimedia terminals. In the last years, the new video coding standards, like High Efficiency Video Coding (HEVC), and the increasing resolutions of video codecs have overtaken the capacities of the single core processors in embedded systems. In consequence, multicore architectures are used in current multimedia systems. Besides, new methodologies and frameworks are arising to speed-up the design cycle. In this paper, a methodology based on the Reconfigurable Video Coding CAL Actor Language (RVC-CAL) and the OpenMP API has been used to implement an HEVC decoder based on a multicore DSP. A RVC-CAL description of the HEVC decoder has been used as starting point. The Open RVC-CAL compiler framework (Orcc) has been used to generate C-code from the RVC-CAL specification. This code and the OpenMP library have been ported to the multicore DSP environment. Decoders running on 1, 2, 3 and 4 cores have been tested. Also, the multi DSP based HEVC decoder has been compared with other implementations based on multicore GPPs.

A multicore DSP HEVC decoder using an actorbased dataflow model and OpenMP

Review of various reduced-complexity min-sum based decoding algorithms for LDPC codes are presented. New BP-based approach for LDPC decoding was proposed, and one new a-min∗-min decoding algorithm was presented. Complexity, effectiveness, and average number of iteration for each algorithm are shown.

Min-sum algorithm-structure based decoding algorithms for LDPC codes

Fast Fourier transform (FFT) implementation on the TMS320C66x multicore digital signal processor (DSP) from Texas Instruments is considered in this paper. A FFT parallelization strategy is chosen and an expected performance gain is estimated. The algorithm is implemented in software for a four-core DSP architecture with interactions between cores based on inter-processor communication (IPC) and open multi-processing (OpenMP) techniques. Experimental results for a performance gain dependent on transform size are given. 2.9 times processing time reduction with 4 cores implementation is achieved.

http://ieeexplore.ieee.org/iel7/6917608/6924338/06924356.pdf

Parallel FFT implementation on TMS320c66x multicore DSP

Teaching implementation of digital signal processing systems plays a very important role in recent technical education. The multi-core digital signal processor (DSP) is a new type of architecture widely used now in the industry. A new course on multi-core DSP programming is considered in this paper. The lab experiments are described. The course has been developed for the TMS320C6678 multi-core DSPs. This paper provides educators with a content that cover theoretical and technical skills that are required by industry.

/pdf/teaching-multi-core-dsp-implementation-on-evm-c6678-board-3dwaa5nvp7.pdf

Teaching multi-core DSP implementation on EVM C6678 board

In this paper we explore acceleration of the logarithmic likelihood ratio (LLR) belief propagation (BP) algorithm for LDPC codes decoding simulation, using parallel computation on graphics processing units (GPUs) with OpenCL technology. The proposed parallel implementation of the LLR BP algorithm includes parallel version of all decoding steps: decoder initialization, check and variable nodes update, a posteriori LLR calculation and decoding termination check. Decoder throughput was measured by simulating data transmission system with LDPC coding for DVB-T2/S2 (64800, 32400) and PEG (1008, 504) codes.

Flexible parallel implementation of LLR BP decoding simulation on multicores using OpenCL

Low-density parity-check (LDPC) codes are now widely used in telecommunication systems due to their outstanding performance. LDPC decoding is a very computational intensive procedure and its implementation in real-time and as a part of embedded system is an actual problem. FPGA, GPP or GPU platforms are usually used. In this paper an LDPC belief propagation (BP) decoder is implemented on a DSP+ARM platform. It is shown that the porting of OpenCL software from a GPU or GPP to a DSP+ARM platform requires minimal effort. Additional code modifications to improve the DSP+ARM performance are described. The effectiveness of the platform is demonstrated, with up to 2 decoding iterations executing in real time.

LDPC decoder implementation on DSP+ARM platform with OpenCL

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