Vivek Subramanian
University of California, Berkeley
273 Papers
6.6K Citations
Vivek Subramanian is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Printed electronics & Thin-film transistor. The author has an hindex of 62, co-authored 271 publications. Previous affiliations of Vivek Subramanian include SanDisk & University of Texas at Austin.
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Papers
Patent
Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication
Mark G. Johnson,Thomas H. Lee,Vivek Subramanian,Paul M. Farmwald,James M. Cleeves +4 more
- 06 Dec 2002
TL;DR: In this article, a very high density field programmable memory (FPM) is described. And the array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells.
1.2K
Inkjet-printed line morphologies and temperature control of the coffee ring effect.
Dan Soltman,Vivek Subramanian +1 more
TL;DR: Under appropriate conditions, the coffee ring effect is able to enhance or eliminate in the authors' drying features by controlling the evaporation profile of drying drops and lines.
1K
Hydrothermal synthesis and pseudocapacitance properties of MnO2 nanostructures.
TL;DR: Interestingly, SEM, TEM, and HRTEM revealed a variety of structures ranging from nanostructured surface with a distinct platelike morphology to nanorod depending upon the hydrothermal reaction time employed during the preparation of the manganese oxide: increasing the amount of individual nanorods in the materials prepared with longer hydrother mal reaction time.
957
Printed electronics: the challenges involved in printing devices, interconnects, and contacts based on inorganic materials
Jolke Perelaer,Patrick Smith,Dario Mager,Daniel Soltman,Steven K. Volkman,Vivek Subramanian,Jan G. Korvink,Ulrich S. Schubert +7 more
TL;DR: In this article, the use of metal and metal oxide-containing inks in the preparation of contacts and interconnects is discussed, as well as the challenges associated with processing these types of inks and ways to successfully obtain the desired features.
744
Sub 50-nm FinFET: PMOS
Xuejue Huang,Wen-Chin Lee,C. Kuo,D. Hisamoto,Leland Chang,J. Kedzierski,E. Anderson,Hideki Takeuchi,Yang-Kyu Choi,K. Asano,Vivek Subramanian,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +13 more
- 01 Dec 1999
TL;DR: In this article, a self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect, and a 45 nm gate-length PMOS FinEET is presented.
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