V. Jagan Naveen
GMR Institute of Technology
10 Papers
37 Citations
V. Jagan Naveen is an academic researcher from GMR Institute of Technology. The author has contributed to research in topics: Orthogonal frequency-division multiplexing & Modulation. The author has an hindex of 4, co-authored 10 publications. Previous affiliations of V. Jagan Naveen include Andhra University.
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Papers
•Journal Article
Performance analysis of equalization techniques for MIMO systems in wireless communication
TL;DR: In this paper, the performances of equalization techniques by considering 2 transmit 2 receive antenna case (resulting in a 2×2 MIMO channel) were analyzed in a flat fading Rayleigh multipath channel and the modulation is BPSK.
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New figures of merit for range resolution radar using Hamming and Euclidean distance concepts
K. Raja Rajeswari,Pathipati Srihari,P. Rajesh Kumar,M. Murali,V. Jagan Naveen,G. Manmadha Rao +5 more
- 15 Apr 2007
TL;DR: The figures of merit are calculated up to four noise levels and the deterioration performance is evaluated and indicate the performance of the deterioration rate as the medium gets noisier.
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ICI Reduction using Extended Kalman Filter in OFDM System
TL;DR: The effects of ICI has been analyzed and two solutions to combat ICI have been presented, including a self cancellation scheme, in which redundant data is transmitted onto adjacent subcarriers such that the ICI between adjacent sub carriers cancels out at the receiver.
Performance Comparison of Wiener Filter and CLS Filter on 2D Signals
K. Raja Rajeswari,K. Murali Krishna,V. Jagan Naveen,A. Vamsidhar +3 more
- 27 Apr 2009
TL;DR: The performance of Wiener and (CLS) constrained least square filtering methods are considered on the basis of noise to signal ratios, image power, noise power and histograms on restoration images.
6
Implementation of 32-Point FFT Processor for OFDM System
G. Soundarya,V. Jagan Naveen,D. Tirumala Rao +2 more
- 01 Jan 2015
TL;DR: An implementation of the 32-point FFT processor with radix-2 algorithm in R2MDC architecture is the processing element and this butterfly- Processing Element (PE) used in the32-FFT processor reduces the multiplier complexity by using real constant multiplication in one method and eliminates the multiplicative complexity byUsing add and shift operation in the proposed method.
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