A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

Semiconductor Integrated Circuit Device

A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.

Semiconductor integrated circuit device and microcomputer

PROBLEM TO BE SOLVED: To provide a non-contact type voltage detecting apparatus detecting a detection target AC voltage in a wide region, and also to provide a line voltage detecting apparatus detecting a line voltage between electrical paths in a wide region. SOLUTION: The voltage detecting apparatus: a detecting part 14 for outputting a detection signal S1 of which amplitude is varied in accordance with a potential difference Vdi between an AC voltage V1 of a detection target 4 and a voltage Vr of a guard electrode 11; a reference signal output part 31 outputting a reference signal Ss to the guard electrode 11; an insulation part 15 outputting an insulation detection signal S2 electrically insulated with the input detection signal S1; a feedback control part 37 for amplifying the insulation detection signal S2 so as to reduce the potential difference Vdi to generate a voltage signal S4, and outputting it to the guard electrode 11; and a signal extracting part 32 for controlling a predetermined gain used for amplifying the insulation detection signal S2 so that a first signal component of the reference signal Ss included in an amplification detection signal S3 which is obtained by amplifying the signal S2 with the predetermined gain, and a second signal component of the reference signal Ss included in a reference signal Sr1 based on the voltage Vr are offset by addition of the signals S3 and Sr1, and generating a signal component of the AC voltage V1 from the signals S3 and Sr1 and outputting it as an output signal So. COPYRIGHT: (C)2011,JPO&INPIT

Voltage detecting apparatus and line voltage detecting apparatus

PROBLEM TO BE SOLVED: To provide a semiconductor memory apparatus in which erroneous sensing caused by offset of a sense amplifier can be prevented when operation of a N channel preferential sensing system is performed using a low array voltage. SOLUTION: In this semiconductor memory apparatus, a VBB generating circuit 12 generates back bias voltage VBB to be applied to a pair of first NMOS transistors of a sense amplifier is constituted of a level detecting circuit 20 including a series circuit consisting of a NMOS transistor TN10 of which the operation property is almost the same as the first NMOS transistor, a resistor R1, and a resistor R2, and a comparator 30, a ring oscillator 21, and a charge pump 22, and feedback control is performed so that when Vtn is raised in accordance with threshold value voltage Vtn of the NMOS transistor TN10, an absolute value of the VBB is decreased, when the Vtn is lowered, the absolute value of the VBB is increased. Under such control, sensing operation according to the N channel preferential sensing system is performed. COPYRIGHT: (C)2007,JPO&INPIT

Semiconductor memory apparatus

PURPOSE:To perform the measurement of a reference potential and the detection of a defective memory cell simultaneously by one wafer test. CONSTITUTION:A desired reference potential is measured in a state that the output 3 of a reference-potential generation circuit 10 Is set to a reference potential by setting a pad P1 to a GND. A defective memory is detected by applying a desired potential to the pad P1. At this time, the threshold value of an inverter I1 is set to be lower than the desired potential.

Semiconductor integrated circuit device

PURPOSE:To hold a substrate bias voltage to a fixed level by inserting corrent sources onto both sides of a transistor constituting an inverter constituting a delay circuit and controlling the currents of the current sources with threshold values. CONSTITUTION:When the threshold value of a P channel MOS transistor becomes larger due to the deviation, etc., in a device process, a voltage of a node 10 is made higher, and the currents flowing through the P channel MOS transistor Q4 and N channel MOS transistor Q3 are made larger, and a delay time is shortened. On the contrary, when the threshold value of the P channel MOS transistor becomes smaller, the current flowing through the N channel transistor Q3 constituting a delay inverter circuit 2a is made smaller, and the delay time is prolonged, and an output frequency of a ring oscillator 2 is reduced. In such a manner, by following a charge pump circuit by changing a frequency in response to the change in the threshold value of the transistor, fixed bias power is outputted always.

Substrate bias circuit

PROBLEM TO BE SOLVED: To provide a method for photographing the grounded shape of a tire during travel of a vehicle on a wet road surface ensuring that the grounded shape and the behavior of the tire can be observed by projecting images clearly. SOLUTION: When the grounded shape 8 of the tire 7 traveling on a transparent plate 3 having a water film is photographed from beneath the transparent plate 3, a water film 6 of an aqueous solution wherein the concentration of a white (N9) or reddish yellow (hue signs of 7YR to less than 2Y, lightness value of 5 or more, saturation value of 4 or more) or yellow (hue signs of 2Y to less than 6Y, lightness value of 6 or more, saturation value of 4 or more) pigment is 2 to 10 wt.% is formed on the transparent plate 3 and the tire 7 is caused to travel on the transparent plate 3 coated with the water film 6 of the aqueous solution mixed with the pigment; the grounded shape 8 of the tire is photographed from beneath by a video camera 4.

Method for photographing grounded shape of tire during travel of vehicle on wet road surface

PROBLEM TO BE SOLVED: To reduce the number of wiring of a sense amplifier section and to reduce a chip area by using commonly a dummy word line and a data bus for writing in a gate receiving system. SOLUTION: A difference point between this circuit configuration and conventional circuit configuration is that a dummy word line is eliminated, a capacity element C2 is arranged between a data bus WBSN for writing and a bit line BLN, and a capacity element C3 is arranged between a data bus WBST for writing and a bit line BLT. Thereby, in this circuit, two pieces of wiring are decreased, comparing with a conventional circuit. Thus, a data bus for writing and a dummy word are used commonly in this circuit configuration, but circuit configuration is completely the same as a conventional circuit configuration in circuit operation.

Dynamic type semiconductor memory circuit device

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