Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of route-segment ends) on a particular layer based on the routing directions available on the particular layer. By so defining these shapes, these embodiments improve the alignment of route segments that have differing widths. In other words, dynamically defining the interconnect-line ends improves the shape of a route at bends along which the route transition from one width to another. Also, to facilitate the creation of a route with different widths and/or spacing in different directions on a particular layer, some embodiments define, for each available routing direction on the particular layer, an “unroutable” bloated region about a previously defined geometry (e.g., a previously defined obstacle, wire, or via pad) on the particular layer. An item's bloated region for a particular routing direction specifies the portion of the particular layer that is not available for route segments along the particular routing direction. As further described below, the item's bloated region for a particular direction is derived based on the minimum spacing required between the item and any route segment in the particular direction for the particular net.

Method and apparatus for routing

Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It then defines a particular route for each particular net in the set of nets, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in the different directions on the same layer.

Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts

This paper presents a high-quality very large scale integration (VLSI) global router in X-architecture, called XGRouter, that heavily relies on integer linear programming (ILP) techniques, partition strategy and particle swarm optimization (PSO). A new ILP formulation, which can achieve more uniform routing solution than other formulations and can be effectively solved by the proposed PSO is proposed. To effectively use the new ILP formulation, a partition strategy that decomposes a large-sized problem into some small-sized sub-problems is adopted and the routing region is extended progressively from the most congested region. In the post-processing stage of XGRouter, maze routing based on new routing edge cost is designed to further optimize the total wire length and mantain the congestion uniformity. To our best knowledge, XGRouter is the first work to use a concurrent algorithm to solve the global routing problem in X-architecture. Experimental results show that XGRouter can produce solutions of higher quality than other global routers. And, like several state-of-the-art global routers, XGRouter has no overflow.

XGRouter: high-quality global router in X-architecture with particle swarm optimization

An automated method and system is disclosed to determine an Integrated Circuit (IC) package interconnect routing using a mathematical topological solution. A global topological routing solution is determined to provide singular ideal IC package routing solution. Topological Global Routing provides a mathematical abstraction of the problem that allows multiple optimizations to be performed prior to detailed routing. Preliminary disregard of electrical routing segment width and required clearance allows the global topological solution to be determined quickly. The global topological solution is used in conjunction with necessary design parameters to determine the optimal geometric routing solution. Guide points are determined using the geometric routing solution. A detail router uses the guide points as corners when performing the actual routing.

Topological global routing for automated ic package interconnect

One embodiment of the invention is a method of specifying routes for a group of nets. The method specifies a total cost. It then performs a first depth-first search to identify, for the group of nets, a complete routing solution that has a cost that does not exceed the total cost. A routing solution for a set of nets includes a route for each net in the set. If the search does not find the complete routing solution, the method then increments the total cost and performs a second depth-first search to identify a complete routing solution for the group of nets that has a cost that does not exceed the incremented total cost.

Method and apparatus for routing a set of nets

Due to the large number of I/O’s in a BallGrid-Array (BGA) package, routing becomes more and more an important work. A ring-based router for the BGA package is presented in this paper to interconnect each I/O pad of a chip to a corresponding ball distributed on the substrate area. The major phases for the router consist of layer assignment, topological routing, and physical routing. Using this router, we can generate an even distribution of planar and any-angle wires to improve manufacturing yield. We have also conducted various testing examples to verify the efficiency of this router. Experiments show that the router produces very good results, far better than the manual design, thus it can be applied to the practical packaging of integrated circuits. key words: ball grid array (BGA), pin grid array (PGA), inversion table

A New Approach to the Ball Grid Array Package Routing

High performance buffered x-architecture zero-skew clock tree construction with via delay consideration

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A New Approach to the Ball Grid Array Package Routing

High performance buffered x-architecture zero-skew clock tree construction with via delay consideration