Tokuo Kure
Hitachi
184 Papers
3.1K Citations
Tokuo Kure is an academic researcher from Hitachi. The author has contributed to research in topics: Etching (microfabrication) & Transistor. The author has an hindex of 32, co-authored 184 publications. Previous affiliations of Tokuo Kure include Renesas Electronics.
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Papers
Patent
Dry etching by alternately etching and depositing
Sadayuki Okudaira,Hiroshi Kawakami,Tokuo Kure,Kazunori Tsujimoto,Shinichi Tachi +4 more
- 06 Oct 1989
TL;DR: In this article, a dry etching method including the steps of introducing etching and deposition gases alternately into a reaction chamber at predetermined time intervals, etching the exposed surface of an article to be etched and applying deposition to the surface film thereof alternately, is characterized in that the power is applied after the passage of predetermined time from the start of the introduction of the deposition gas and before the etching gas is introduced and cut off when the introduction is suspended.
195
Single-electron memory for giga-to-tera bit storage
Kazuo Yano,Tomoyuki Ishii,T. Sano,Toshiyuki Mine,Fumio Murai,Takayuki Hashimoto,T. Kobayashi,Tokuo Kure,Koichi Seki +8 more
- 01 Apr 1999
TL;DR: These are the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration and its positioning among various memory architectures.
189
Single-electron memory for giga-to-tera bit storage : Special issue on quantum devices and their applications
Kazuo Yano,Tomoyuki Ishii,T. Sano,Toshiyuki Mine,Fumio Murai,Takayuki Hashimoto,T. Kobayashi,Tokuo Kure,Koichi Seki +8 more
- 01 Jan 1999
TL;DR: In this paper, the authors address the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration, including room-temperature operation, memory-cell architecture, sensing scheme, cell-design guideline, use of nanocrystalline silicon versus lithography, array architecture, device to device variations, read/write error rate, and its positioning among various memory architectures.
153
A semi-static complementary gain cell technology for sub-1 V supply DRAM's
TL;DR: In this article, a semi-static complementary gain cell for low power DRAM's is proposed and experimentally demonstrated, which consists of a write-transistor and its opposite conduction type read-transistors with a heating gate as a storage node which causes a shift in the threshold voltage.
146
Patent
Semiconductor memory device having stacked capacitor cells
Shinichiro Kimura,Naotaka Hashimoto,Yoshio Sakai,Tokuo Kure,Yoshifumi Kawamoto +4 more
- 21 Dec 1988
TL;DR: In this article, the bit lines are shielded, the capacitance between bit lines decreases, and the memory array noise decreases, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas.
112