An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

The present invention provides a method for manufacturing a semiconductor structure, comprising: a) forming metal interconnect liners on a substrate; b) forming a mask layer to cover the metal interconnect liners and forming openings, which expose the metal interconnect liners, on the mask layer; c) etching and disconnecting the metal interconnect liners via the openings, thereby insulating and isolating the metal interconnect liners. The present invention further provides a semiconductor structure, which comprises a substrate and metal interconnect liners, wherein ends of the metal interconnect liners are disconnected by insulating walls formed within the substrate. The structure and the method provided by the present invention are favorable for shortening distance between ends of adjacent metal interconnect liners, saving device area and suppressing short circuits happening to metal interconnect liners.

Semiconductor structure and method for manufacturing the same

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

Semiconductor device having doped epitaxial region and its methods of fabrication

A semiconductor device includes a substrate including an active region, a gate structure, source/drain regions, ones of the source/drain regions having an upper surface in which a recessed region is formed, a contact plug on the source/drain regions and extending in a direction substantially perpendicular to an upper surface of the substrate from an interior of the recessed region, a metal silicide film on an internal surface of the recessed region and including a first portion between a bottom surface of the recessed region and a lower surface of the contact plug and a second portion between a side wall of the recessed region and a side surface of the contact plug, and a metal layer connected to an upper portion of the metal silicide film and on a side surface of a region of the contact plug.

Semiconductor devices having reduced contact resistance

By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.

Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain

By performing a silicidation process on the basis of a patterned dielectric layer, such as an interlayer dielectric material, the respective metal silicide portions may be provided in a highly localized manner at the respective contact regions, while the overall amount of metal silicide may be significantly reduced. In this way, a negative influence of the stress of metal silicide on the channel regions of field effect transistors may be significantly reduced, while nevertheless maintaining a low contact resistance.

A transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same

A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.

Methods for fabricating an integrated circuit

A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

Contacts and vias of a semiconductor device formed by a hard mask and double exposure

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