The local backlight dimming technology has recently been presented for liquid crystal displays in order to reduce the power consumption of backlight and improve the quality of the display. Therefore, exploiting the tradeoff between the image quality and power consumption has become the focus of local backlight dimming technology. This paper considers the local backlight dimming as an optimization problem, i.e., how to preserve the image quality perception with a certain low backlight power consumption. To achieve this goal, we use the swarm intelligence algorithm. Specifically, an improved shuffled frog leaping algorithm is proposed for local backlight dimming. Simulation results show that the proposed algorithm achieves the better tradeoff between power consumption and image quality when compared to other algorithms based on image parameters.

Optimal Local Dimming Based on an Improved Shuffled Frog Leaping Algorithm

A shift register for flat panel display devices includes a start signal unit configured to control a start of an output signal, an end signal unit configured to control an end of the output signal, and a plurality of stages configured to increase the output signal to a high-level driving voltage according to a signal supplied from a first node connected to the start signal unit, and decrease the output signal to a low-level driving voltage according to a signal supplied from a second node connected to the end signal unit. Each of the plurality of stages generates multi signals for diving a pixel circuit of a display device.

Shift register and method of driving the same

A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to -40 °C is proposed and demonstrated. The carry signal (C N ) of the driver, being generated through the voltage bootstrapping approach using a C N -connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of C N is much shorter than that of the gate driving signal G N , the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver’s malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the G N , instead of C N , is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 μm×1099 μm. Measurements show that the output voltage magnitude can be maintained well when temperature varies from -40 °C to 80 °C. Moreover, the rising-time and falling-time increase of the output pulse are both less than 3 μs after 240 hours of the accelerated high temperature aging operations.

A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

A TFT array substrate is disclosed. The substrate includes a plurality of gate lines, and a first gate drive circuit, where the first gate drive circuit includes m levels of first repeat units. Each level of first repeat unit includes a first shift register. The substrate also includes a second gate drive circuit, where the second gate drive circuit includes n levels of second repeat units. Each level of second repeat unit includes a second shift register. The substrate also includes a first start signal line and a first start transistor, where a drain of the first start transistor is electrically connected with the first start signal line. The substrate also includes a second start transistor, where a drain of the second start transistor is electrically connected with the first start signal line.

Tft array substrate, display panel and display device

The invention relates to a pixel structure for autostereoscopic display. The pixel structure comprises a main display area of sub-pixels and a crosstalk area of the sub-pixels. The brightness of the main display area and the brightness of the crosstalk area are controlled separately. The invention further relates to the array substrate for use with an oblique grating; the array substrate comprises a substrate body, a plurality of data lines and gate lines, and the pixel structures arrayed on the substrate body; at least part of the array of the pixel structures are equal to the pixel structure above; image arrangement of the sub-pixels of the array of the pixel structures is oblique correspondingly, during autostereoscopic display. The invention further relates to a method of controlling the pixel structures of the array substrate.

Pixel structure, array substrate, control method of array substrate and display device

Embodiments of the invention relate to a stereoscopic image display and a method for driving the same. Stereoscopic image display includes a data display unit including a first scan transistor, an active black stripe unit including a second transistor and a third transistor, and a shift register sequentially supplying the gate pulse to each of (2n−1)th gate lines and (2n)th gate lines, where n is a natural number. The first scan transistor supplies a data voltage to a pixel electrode in response to a gate pulse of a (2n−1)th gate line, the second transistor supplies the data voltage to the pixel electrode in response to the gate pulse of the (2n−1)th gate line, and the third transistor supplies a low logic level voltage or a common voltage to the pixel electrode in response to a gate pulse of a (2n)th gate line.

Stereoscopic image display and method for driving the same

The 120Hz frame inversion driving FHD LCD TV panels were fabricated without image degradations seen such as the luminance gradient and the horizontal crosstalk. The panels had the higher aperture ratio because of the wider electrode space between the pixel and common electrode than conventional S-IPS. The novel driving method of gate-low-voltage-swing was used to remove the luminance gradient and the new panel design of divided-common-feeding was adopted to suppress the horizontal crosstalk. These technologies were very successful to achieve the high aperture ratio in the S-IPS panel without increase of the panel cost.

26.4: Novel Driving and Panel Design of Frame Inversion Method for High Aperture Ratio in the Large Size and High Resolution LCD TV Panel

This paper presents a new 2D–3D switchable driving method for a 3D thin-film transistor liquid crystal display (TFT-LCD) TV. The proposed driving method, which uses a film-type patterned retarder (FPR), can reduce unnecessary power consumption while displaying 2D images. The proposed driving method can change a part of a pixel according to the driving mode; the part is operated as a black matrix in a 3D display mode, whereas in a 2D display mode, the part is operated as a normal pixel. To realize the proposed driving method without increasing the data signal rates, the number of gate driver integrated circuits (ICs), and the bezel size of the panel, a novel pixel structure and an integrated a-Si:H gate driver, which can be implemented in a small size, are developed. The power consumption of the proposed driving method measured at the full white gray level is 67 W in a 47-in full-high-definition (FHD) TFT-LCD TV. This result shows that the power consumption of the proposed driving method decreases by 28% compared with that of the conventional driving method in the 2D display mode.

A 2D-3D Switchable Driving Method for Reducing Power Consumption of Thin-Film Transistor Liquid Crystal Display TV With Film-Type Patterned Retarder

In case of using an a-Si:H integrated gate driver for TFT-LCD [1–4], it's important to define gate falling time exactly. Because an a-Si:H integrated gate driver might degrade with bad environment easily, which result in gate signal delay or decreasing output signal. In other words, a little degradation of a-Si:H gate driver affects the quality of picture. If a little degradation of a-Si:H gate driver under special circumstance is inevitable, it's necessary to make a gate driver has so sufficient margin time within one horizontal time that cannot be interfered with next data signal. So, it's necessary to understand what factors affect the a-Si:H integrated gate output signal. Especially, we focused an a effect of buffer transistor resistance for gate output signal. In our study, with a test a-Si:H integrated gate driver pattern and simple simulation process, a relation a-Si:H integrated buffer transistor resistance and gate output signal is analyzed.

P-30: A Relation Between an a-Si: H Integrated Buffer Transistor Resistance and Falling Time of Gate Output Signal

A liquid crystal display device includes a data analysis unit to analyze image data of an input image data stream for variation of luminance between the image data, a black data processing unit to insert black data into the input image data stream based on the variation of luminance analyzed by the data analysis unit and to output an output image data stream, and a liquid crystal panel to display images based on the output image data stream output from the black data processing unit

Liquid crystal display device including a data analysis unit and method for driving the same

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