With increasing integration densities, large chip designs are commonly partitioned into multiple clock domains. While the computation within each individual domain may be synchronous, the interfaces between these domains often use asynchronous methods. One such approach is the STARI technique where a self-timed FIFO compensates for clock-skew between the sender and receiver. We present implementations of STARI where the FIFO consists of a single, handshaking stage. We start with the simplest case where the sender and receiver operate at exactly the same frequency with an unknown skew. We then generalize this design for links with clocks whose frequencies are rational multiples of each other, clocks whose frequencies are closely matched, and arbitrary clocks. We show that in each of these cases, the STARI interface can exploit the stability of typical clocks to achieve low latencies and negligible probabilities of synchronization failure using very simple hardware.

/pdf/efficient-self-timed-interfaces-for-crossing-clock-domains-7ksm4aejvl.pdf

Efficient self-timed interfaces for crossing clock domains

A leakage-biased domino circuit family is proposed that maintains high speed in active mode but which can be rapidly placed into a low-leakage inactive state by using leakage currents themselves to bias internal nodes. A 32-bit Han-Carlson domino adder circuit is used to compare LB-domino with conventional single and dual Vt domino circuits. For equal delay and noise margin, the LB-domino technique gives two decades reduction in steady-state leakage energy compared to a dual-Vt technique.

/pdf/leakage-biased-domino-circuits-for-dynamic-fine-grain-46knt51aay.pdf

Leakage-biased domino circuits for dynamic fine-grain leakage reduction

Taking full advantage of the high resistivity substrate and underlying oxide of SOI technology, a high performance CMOS SPDT T/R switch has been designed and fabricated in a partially depleted, 0.25µm SOI process. The targeted Bluetooth class II specifications have been fully fitted. The switch over the high resistivity substrate exhibits a 0.7dB insertion loss and a 50dB isolation at 2.4GHz; at 5GHz insertion loss and isolation are 1dB and 47dB respectively. The measured ICP1dBis +12dBm.

http://ieeexplore.ieee.org/iel5/9921/31530/01471570.pdf

A 0.7dB insertion loss CMOS&#8211;SOI antenna switch with more than 50dB isolation over the 2.5 to 5GHz band

This paper proposes computational locking (C-lock) in all-digital phase-locked loops (PLLs) to achieve rapid frequency and phase lock acquisition. The proposed approach employs a “lock-accelerator” module that accelerates lock-times ( $T_{\mathrm{ lock}}$ ) in both cold-start (PLL power-up) and re-lock scenarios without impacting steady-state PLL performance. The key premise underlying C-lock is that solving a system of accurate phase-frequency update equations at run-time provides superior lock performance compared to traditional PLLs that rely on linear feedback control. C-lock is readily amenable to runtime adaptation to Process, Voltage, and Temperature (PVT) variation. A 1–2 GHz computationally locked PLL was implemented in a 65-nm standard CMOS process. Measurements over 50 000 iterations of re-lock and cold-start experiments across multiple test-chips, supply-voltage ( $V_{\mathrm{ dd}}$ ), and operating temperatures indicate a mean re-lock time of 12 PLL reference clock cycles (12 $T_{\mathrm{ REFCLK}}$ ), and a “cold-start” $T_{\mathrm{ lock}}$ of 16 $T_{\mathrm{ REFCLK}}$ . Although the silicon demonstration of C-lock is based on a PLL designed for system clocking applications, the proposed approach is applicable to a broader class of PLLs.

A 1–2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation

PowerTune is a power-management technique for a multi-gigahertz superscalar 64b PowerPC/sup /spl reg// processor in a 90nm technology. This paper discusses the challenges and implementation of a dynamically controlled clock frequency with noise suppression as well as a synchronization circuit for a multi-processor system.

http://ieeexplore.ieee.org/iel5/9264/29428/01332741.pdf

PowerTune: advanced frequency and power scaling on 64b PowerPC microprocessor

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

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A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric