In one aspect, a method of instructing operators in a best practices implementation of a service monitoring and control (SMC) facility performing a plurality of functions in a computer system comprising a plurality of services to be monitored is provided The method comprises an act of providing best practices instructions for the implementation of the SMC facility in a hierarchical manner so that the implementation of the SMC facility is described as comprising a plurality of top level activities to be performed during the operation of the SMC, with each of the plurality of top level activities being described as comprising at least one lower level sub-activity, the top level activities comprising, assessing performance of the SMC facility, in response to information learned during assessing the performance of the SMC facility, implementing at least one change in the SMC facility, monitoring the computer system with the changed SMC facility for an occurrence of at least one event, and automatically performing at least one control action in response to the occurrence of the at least one event In another aspect, a top-level activity of collaborating with one or more developers is described, resulting in a change to at least one change to software executed on the computer system In another aspect, at least a part of the effectiveness of an SMC facility is automatically assessed, and in response, one of the plurality of functions performed by the SMC facility is automatically changed

Methods for service monitoring and control

In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor Other embodiments are described and claimed

Providing per core voltage and frequency control

A system and method for storing infrequently accessed data with reduced power consumption. In one embodiment, a solid state drive (SSD) includes flash memory and environmental data logging circuitry. The SSD is shut off or operated in a sleep mode to reduce power consumption, and turned on or transitioned to an active mode as needed when data on the SSD is to be accessed, or when a calculation, based on a number of erase cycles previously performed in the flash memory and on a temperature history of the SSD indicates that a data refresh may be needed to prevent data corruption in the SSD, due to data retention limitation of the nonvolatile memory in the SSD.

Power efficient method for cold storage data retention management

In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

Dynamically allocating a power budget over multiple domains of a processor

A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may not be updated until after information identifying the instruction is captured. The instruction may be flushed from the pipeline, along with other instructions from the same thread. A hardware trap may be taken when the instruction is detected and/or when an event counter overflows or is within a given range of overflowing. A software trap handler may capture and/or log information identifying the instruction, such as one or more extended address elements, before returning control and initiating a retry of the instruction. The captured and/or logged information may be stored in an event space database usable by a data space profiler to identify performance bottlenecks in the application containing the instruction.

Method and apparatus for precisely identifying effective addresses associated with hardware events

Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

System To Profile And Optimize User Software In A Managed Run-Time Environment

In one embodiment, the present invention is directed to a system that includes an optimization unit to optimize a code segment, and a profiler coupled to the optimization unit. The optimization unit may include a compiler and a profile controller. Further, the profiler may be used to request programming of a channel with a scenario for collection of profile data during execution of the code segment. Other embodiments are described and claimed.

Profiling using a user-level control mechanism

A system and method are described for configuring and collecting performance counter information of a computer system. The method includes providing one or more performance objects, each object containing a predetermined set of events. A user is allowed to select the entire set or a subset of events to be monitored during a collection session from the predetermined set of events contained in the performance objects. The performance counters associated with the subset of events selected are programmed to increment in response to an occurrence of a respective event. The data stored in each of the performance counters associated with the subset of events selected is periodically read during the collection session.

Method and apparatus for configuring and collecting performance counter data

In one embodiment, a method includes, upon occurrence of multiple power state transition events for a core of a multi-core processor, reading a value of a system counter of the core and values of low power counters of the core, without expiration of a timer or triggering of an interrupt. These values can be stored in a storage of the processor. Then, after collection is completed, the storage can be accessed to determine a power profile of the processor using the stored values. Other embodiments are described and claimed.

Obtaining Power Profile Information With Low Overhead

Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Techniques for tracing wakelock usage

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