Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can read and write data at the same time, a typical single-port memory based FIFO cannot. The operation of the two single-port memory banks are coordinated in order to provide similar or better performance than a dual-port memory based FIFO.

Circuitry and methods for efficient FIFO memory

A method is described that forms different pieces of a packet and sends each one of the pieces toward a different memory unit amongst a plurality of memory units. Each one of the memory units is managed by a different network processor. The method also receives each of the different pieces, each of the pieces having been read from its respective memory unit of the plurality of memory units.

Method and apparatus for packet segmentation, enqueuing and queue servicing for multiple network processor architecture

An apparatus is described that includes a plurality of queuing paths. Each of the queuing paths further comprises an input queue, an intermediate queue and an output queue. The input queue has an output coupled to an input of the intermediate queue and the input of the output queue. The intermediate queue has an output coupled to the input of the output queue. The intermediate queue receives data units from the input queue if a state of the input queue has reached a threshold. The output queue receives data units from the intermediate queue if the intermediate queue has data units. The output queue receives data units from the input queue if the intermediate queue does not have data units.

Apparatus and method for queuing flow management between input, intermediate and output queues

According to one embodiment, a method of regulating traffic at a network hardware machine is disclosed. The method includes receiving a data packet, calculating a time stamp difference value, determining whether a maximum token bucket value has been exceeded by the time stamp difference value and determining whether there are enough tokens to transmit the packet.

Method of policing network traffic

According to one embodiment, a network is disclosed. The network includes a source device, a networking hardware machine coupled to the source device, and a destination device coupled to the networking hardware machine. The networking hardware machine receives data packets from the source device and distributes statistics data corresponding to the data packets among multiple internal memory devices.

Mechanism for distributing statistics across multiple elements

A FIFO memory device is shown which uses embedded logic and DRAM on the same chip. A memory controller controls the transfer of data from input and to output ports to match the access speed of the DRAM to the input and output requirements for the FIFO system. High speed FIFO performance can thus be obtained from relatively high density, low cost and slow access DRAM. The FIFO products that result from this technology will be far less expensive to manufacture.

Fifo memory device using shared reconfigurable memory block

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Fifo memory device using shared reconfigurable memory block