Energy efficiency is the new fundamental limiter of processor performance, way beyond numbers of processors.

/pdf/the-future-of-microprocessors-15i7iemtj8.pdf

The future of microprocessors

Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

/pdf/system-level-analysis-of-fast-per-core-dvfs-using-on-chip-3icz0auash.pdf

System level analysis of fast, per-core DVFS using on-chip switching regulators

Future many-core processors will require high-performance yet energy-efficient on-chip networks to provide a communication substrate for the increasing number of cores. Recent advances in silicon nanophotonics create new opportunities for on-chip networks. To efficiently exploit the benefits of nanophotonics, we propose Firefly - a hybrid, hierarchical network architecture. Firefly consists of clusters of nodes that are connected using conventional, electrical signaling while the inter-cluster communication is done using nanophotonics - exploiting the benefits of electrical signaling for short, local communication while nanophotonics is used only for global communication to realize an efficient on-chip network. Crossbar architecture is used for inter-cluster communication. However, to avoid global arbitration, the crossbar is partitioned into multiple, logical crossbars and their arbitration is localized. Our evaluations show that Firefly improves the performance by up to 57% compared to an all-electrical concentrated mesh (CMESH) topology on adversarial traffic patterns and up to 54% compared to an all-optical crossbar (OP XBAR) on traffic patterns with locality. If the energy-delay-product is compared, Firefly improves the efficiency of the on-chip network by up to 51% and 38% compared to CMESH and OP XBAR, respectively.

/pdf/firefly-illuminating-future-network-on-chip-with-34qvzibkvg.pdf

Firefly: illuminating future network-on-chip with nanophotonics

Device Assisted Services (DAS) for protecting network capacity is provided. In some embodiments, DAS for protecting network capacity includes monitoring a network service usage activity of the communications device in network communication; classifying the network service usage activity for differential network access control for protecting network capacity; and associating the network service usage activity with a network service usage control policy based on a classification of the network service usage activity to facilitate differential network access control for protecting network capacity.

Device-Assisted Services for Protecting Network Capacity

A method performed by an end user device associated with a service plan having a limit on usage of a network service, the method comprising storing one or more notification actions corresponding to one or more notification requests; performing a device action that reflects a past or intended use of the network service; receiving one of the one or more notification requests from a network element in response to the device action; performing one of the one or more notification actions in response to the notification request, the notification action causing the end user device to retrieve at least a portion of a notification message associated with a status of the use, the at least a portion of the notification message being separate from the one of the one or more notification requests; and presenting the notification message on a user interface of the end user device.

System and Method for Providing User Notifications

The TILE64TM processor is a multicore SoC targeting the high-performance demands of a wide range of embedded applications across networking and digital multimedia applications. A figure shows a block diagram with 64 tile processors arranged in an 8x8 array. These tiles connect through a scalable 2D mesh network with high-speed I/Os on the periphery. Each general-purpose processor is identical and capable of running SMP Linux.

TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores.

Computing in parallel processing environments

The present invention provides a method and system for routing a group of scan chains to a group of processor resources in a semiconductor chip. The group of processor resources is arranged in rows or columns. The group of processor resources in each row or column is connected through a plurality of scan chains. The first processor resource in each row or column is connected to input scan-chain pins, and the last processor resource in each row or column is connected to output scan-chain pins. A test-pattern generator, generating test signals, sends the test signals to the group of processor resources by using the group of scan chains within the semiconductor chip. The responses of the processor resources corresponding to the test signals are analyzed to detect and locate any error in the manufacture of the semiconductor chip.

Method and system for routing scan chains in an array of processor resources

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TILE64 - Processor: A 64-Core SoC with Mesh Interconnect

Computing in parallel processing environments

Method and system for routing scan chains in an array of processor resources