A parallel associative memory provides a way of recognizing or identifying observed data patterns. Each of a plurality of memories stores a plurality of recognition patterns. In response to receipt of a recall pattern to be identified, the recall pattern is contemporaneously compared to the recognition patterns stored in the memories and an exact or best match recognition pattern is selected. In a preferred embodiment, the memories may store multiple data bases each of which includes patterns having different lengths and different radii of attraction. The comparison process is controlled by masks which specify respective portions of the patterns which may include the radii of attraction, bits which must identically match, bits which are ignored, bits which are compared in a bit-wise fashion, and bytes which are compared by multiplication. A correlation is computed and selectively adjusted by the respective radii of attraction. A specified number of the patterns having the best correlation are identified, subject to selected threshold conditions, and sorted according to their respective correlations. The parallel nature of the memory lends itself to a hierarchical organization for increased storage capacity and to parallel processing which increases the speed of the identification or recognition process and thereby allows a broad range of applications. These applications includes fast retrieval of exact or inexact data, diagnosis, image processing and speech recognition.

Parallel associative memory having improved selection and decision mechanisms for recognizing and sorting relevant patterns

A machine-implemented process, and apparatus, for performing a set membership test on large sets through the technique of binary hash coding with a known allowable expectation of an error. The present invention does not employ content addressable memory; rather, the present invention performs set membership testing by utilizing a hash function, which produces a randomized plurality of simple address locations within a bulk memory, for each item in the set. A testing for membership comprises employing a logical AND operation upon all values of binary indicators at memory locations addressed by hash values of a test item, to determine whether each and every hash value generated for the test item exactly matches with previously loaded indicators at those address locations in the bulk memory, which in the pereferred embodiment is of the CCD type. The present invention is a machine-implemented process, and employs a known algorithm as part of the overall process. The present invention also essentially comprises synergistic interaction of a hardware item called a "hash board", and a bulk memory. The hash board generates a large number of hash addresses for any given item, using minimal computation time. The expected error rate is a function of the vocabulary size and the total number of indicators in the bulk memory. The bulk memory allows a low error rate for large vocabularies without exceeding the statistically ideal loading density of 50 percent. The hashing technique, together with its hardware implementation, allows a black box approach to general set membership testing. Information stored in the bulk memory can be said to be encrypted because the randomizing process makes it impossible to retrieve the original set of items. A preferred embodiment of the machine-implemented process, and apparatus is for on-line spelling checking of each word which appears in daily newspaper production, against a selective 20,000-word vocabulary, previously stored as a randomized set of simple bit addresses.

Method and apparatus for testing membership in a set through hash coding with allowable errors

A block associative memory includes a plurality of memory cell arrays (70 and 72) arranged in rows and columns. Addressing of memory cells in the arrays (70 and 72) loads the data contained in one row thereof into a row of sense amplifiers (74). The selected row constitutes a block of memory. The data in the accessed block is compared with key data from a key data generator (20) in an equalizer circuit (90). The data in a given row or block is arranged in word groups. Each word group is compared with the key data and a match output generated for each data word group matching the key data word group. This match is decoded to output the column location of that word. The steps of retrieving the block from memory and associating the block with the key search data is performed in a single step and then additional blocks are selected for association with the key data word.

Block associative memory

A method and apparatus are present for monitoring a platform. Information from monitoring the platform is received from a sensor network and a number of systems associated with the platform. A plurality of observations is formed from the information. A profile is created from the plurality of observations in which the profile is used to monitor the platform.

Platform health monitoring system

A semiconductor memory circuit is arranged with an ordinary crosspoint row-column array of dynamic capacitor memory storage cells. Word serial content addressing is enabled by adding a separate combinational logic device, only one such device for each entire column bit line, typically comprising a comparator feeding a NAND gate to which masking data can be supplied.

Content addressable semiconductor memory arrays.

An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAM's), which may be written into, or read from in conventional fashion. In a recognition mode, information is read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor. In accordance with specific aspects of the present invention, masking and/or multiwrite features are provided to permit bit reading/writing/searching, rapid memory writing, to facilitate logical and arithmetic data processing and the like.

Recognition memory with multiwrite and masking

An improved associative memory employs plural separately addressable memories, e.g., random access memories (RAMs), which may be written into, or read from in conventional fashion. In a recognition mode, information is sequentially read from differing memory locations, and compared with an operand supplied on a data bus by a central processing unit (CPU), comparator apparatus being common for an array of storage locations. The comparison results, determined in accordance with a CPU-specified criterion, are then communicated back to the processor.

Associative memory device with variable recognition criteria

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Recognition memory with multiwrite and masking

Associative memory device with variable recognition criteria