Rabab Bouziane

TL;DR: This paper targets emerging nonvolatile memories (NVMs), through Spin-Transfer Torque RAM (STT-RAM), which inherently have quasi-null leakage, which enables to reduce the static power consumption, which tends to become dominant in modern systems.

TL;DR: This paper presents an empirical impact analysis of the integration of Spin Transfer Torque Magnetic Random Access Memory technologies in multicore architectures when applying some existing compiler optimizations, and identifies how the choice of the clock frequency impacts the relative efficiency of the considered memory technologies.

TL;DR: This paper proposes an approach to estimate partial WCET (pWCET), i.e., the worst-case execution time between two locations in a function, such as basic blocks or instructions, derived from the well-known implicit path enumeration technique.

TL;DR: A number of compile-time analysis and optimization techniques are reviewed, and how they could apply to systems in presence of NVMs, including the case of the reduction of the number of writes, and the analysis of variables lifetime for memory bank assignment of program variables.