R. Tsuchihashi
NTT DoCoMo
3 Papers
105 Citations
R. Tsuchihashi is an academic researcher from NTT DoCoMo. The author has contributed to research in topics: Low-power electronics & Power domains. The author has an hindex of 3, co-authored 3 publications.
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Papers
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor
Toshihiro Hattori,T. lrita,Masayuki Ito,Eiji Yamamoto,Hiromu Kato,G. Sado,Y. Yamada,Kunihiko Nishiyama,H. Yagi,T. Koike,Y. Tsuchihashi,M. Higashida,Hiroyuki Asano,I. Hayashibara,Ken Tatezawa,Yasuhisa Shimazaki,Naozumi Morino,K. Hirose,Saneaki Tamaki,S. Yoshioka,R. Tsuchihashi,N. Arai,T. Akiyama,K. Ohno +23 more
- 18 Sep 2006
TL;DR: A power-management scheme for a single-chip multi-CPU processor uses 20 power domains and enables the minimization of leakage currents in each operating mode: 299muA in paging operation and 7 muA in stand-by.
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Hierarchical power distribution and power management scheme for a single chip mobile processor
Toshihiro Hattori,Takahiro Irita,Masayuki Ito,Eiji Yamamoto,Hiromu Kato,G. Sado,T. Yamada,Kunihiko Nishiyama,H. Yagi,T. Koike,Y. Tsuchihashi,M. Higashida,Hiroyuki Asano,I. Hayashibara,Ken Tatezawa,S. Shimazaki,Naozumi Morino,Y. Yasu,Tadashi Hoshi,Y. Miyairi,Kazumasa Yanagisawa,K. Hirose,Saneaki Tamaki,S. Yoshioka,Tatsuki Ishii,Yusuke Kanno,Hiroyuki Mizuno,Tetsuy. Yamada,Naohiko Irie,R. Tsuchihashi,N. Arai,T. Akiyama,K. Ohno +32 more
- 24 Jul 2006
TL;DR: A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described that can achieve very low leakage current in the partial active mode of a single chip mobile processor.
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A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS
Masayuki Ito,Toshihiro Hattori,Takahiro Irita,Ken Tatezawa,F. Tanaka,K. Hirose,S. Yoshioka,K. Ohno,R. Tsuchihashi,M. Sakata,M. Yamamoto,Y. Aral +11 more
- 18 Jun 2007
TL;DR: A single-chip 11.15times11.15mm2 application and dual-mode WCDMA/HSDPA and GSM/EDGE baseband processor achieves 390MHz in triple-V, low-power 90nm 8M CMOS to reduce power consumption and leakage current.
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