Presented are embodiments of methods and systems for library-based compilation and dispatch to automatically spread computations of a program across heterogeneous cores in a processing system. The source program contains a parallel-programming keyword, such as mapreduce, from a high-level, library-oriented parallel programming language. The compiler inserts one or more calls for a generic function, associated with the parallel-programming keyword, into the compiled code. A runtime library provides a predicate-based library system that includes multiple hardware specific implementations (“variants”) of the generic function. A runtime dispatch engine dynamically selects the best-available (e.g., most specific) variant, from a bundle of hardware-specific variants, for a given input and machine configuration. That is, the dispatch engine may take into account run-time availability of processing elements, choose one of them, and then select for dispatch an appropriate variant to be executed on the selected processing element. Other embodiments are also described and claimed.

Compiler and Runtime for Heterogeneous Multiprocessor Systems

Methods and systems are provided for recognizing and processing reduction operations to optimize generated binary code for execution in a multiprocessor computer system. Reduction operations facilitate data parallelism whereby each processing thread contributes a value and the values are reduced using a function to obtain and return a reduced value to each of the threads. Embodiments of an idiom-based interprocedural compiler provide a unified framework for processing both implicit and explicit reductions. The compiler integrates explicit reductions and implicit reductions by providing a uniform intermediate format. The compiler resolves dependencies among processing threads within program code by checking for privatization of dependent threads or parallelizing reduction idioms within the threads, and generates parallelized object code for execution in a multiprocessor computer.

System and method for generating object code for map-reduce idioms in multiprocessor system

A device for performing parallel processing includes a processor to initiate a single programming language, and identify, via the single programming language, one or more data distribution schemes for executing a program. The processor also transforms, via the single programming language, the program into a parallel program with an optimum data distribution scheme selected from the one or more identified data distribution schemes, and allocates the parallel program to two or more labs for parallel execution. The processor further receives one or more results associated with the parallel execution of the parallel program from the two or more labs, and provides the one or more results to the program.

Device for performing parallel processing of distributed arrays

Tasks for a business process can be decomposed into subtasks represented by messages. Message processing can be throttled in a heterogeneous environment. For example, message processing at subtask nodes can be individually throttled at the node level by controlling the number of instances of subtask processors for the subtask node. An infrastructure built with framework components can be used for a variety of business process tasks, separating business logic from the framework logic. Thus, intelligent scalability across platform types can be provided for large scale business processes with reduced development time and resources.

Task decomposition with throttled message processing in a heterogeneous environment

An apparatus and method that use an associative calculator for calculating a sequence of non-associative operations on a set of input data, comprising: using the associative calculator to calculate from the set of input data an evaluated value of each operation of said sequence as if the non-associative operations were associative operations; detecting if some of the evaluated values are erroneous; if there are erroneous evaluated values, correcting the erroneous evaluated values; and if there are no erroneous evaluated value, outputting as the result of the sequence of non-associative operations the evaluated value of the last operation of the sequence.

Method and a circuit using an associative calculator for calculating a sequence of non-associative operations

Methods, systems, and computer readable storage medium embodiments for configuring a lookup table for a network device are disclosed. Aspects in these embodiments include generating a decision tree based upon bit representations of respective data entries from a plurality of data entries where one or more of the plurality of data entries are represented at respective nodes of the decision tree, storing a first bit pattern corresponding to a selected node from the decision tree in a content addressable memory (CAM) at a location associated with an index, and storing one or more second bit patterns at an address in a second memory. The one or more second hit patterns correspond to the one or more data entries represented at the selected node, and the address is associated with the index. Embodiments also include searching a lookup table in a network device.

Hybrid Memory for Search Operations

One embodiment of the present invention provides a system that supports parallelized generic reduction operations in a parallel programming language, wherein a reduction operation is an associative operation that can be divided into a group of sub-operations that can execute in parallel. During operation, the system detects generic reduction operations in source code. In doing so, the system identifies a set of reduction variables upon which the generic reduction operation will operate, along with a set of initial values for the variables. The system additionally identifies a merge operation that merges partial results from the parallel generic reduction operations into a final result. The system then compiles the program's source code into a form which facilitates executing the generic reduction operations in parallel. By supporting the parallel execution of such generic reduction operations in this way, the present invention extends parallel execution for reduction operations beyond basic commutative and associative operations such as addition and multiplication.

Parallelization scheme for generic reduction

Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device.

Organizing data in a hybrid memory for search operations

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Hybrid Memory for Search Operations

Parallelization scheme for generic reduction

Organizing data in a hybrid memory for search operations