Chip-to-wafer interconnect approach is to produce denser and smaller dies, while improving inter-chip bandwidth and power dissipation. In this work a vertical system integration is done by copper pillar and solder interconnects. Three-dimensional (3D) integration technology uses chip-to-wafer bonding to achieve effective chip integration. By structural simulation and modeling a reliable package selection is made from different package designs, epoxy mold compounds (EMC), polymer dielectric (PD) materials and different other package parameters. In this simulation and modeling an approach has been taken to model two levels of solder interconnects namely copper pillar solder micro-bump and BGA (ball grid array) solder in the same FEA (finite element analysis) model. FEA mesh densities in 1 st and 2 nd interconnects are joined by contact pair definition. Parametric studies are done for three different EMC and three different PD materials. 1 st level solder interconnect or micro-bump temperature cycling (TC) reliability life is significantly higher than 2 nd level solder interconnect due to presence of EMC around the 1 st level interconnect. High CTE (coefficient of thermal expansion) of EMC shows very poor solder life for 1 st level solder interconnect. PD material CTE shows significant impact on component side solder life for 2 nd level interconnect. Also, higher PD material CTE shows worsening 1 st level interconnect life. Stress analysis shows pad diameter smaller than UBM (under bump metallization) opening is a better design.

Board level FEA reliability and stress modeling for chip-to-wafer bonded chiplet package

Review of chiplet-based design: system architecture and interconnection

Semiconductor Industry, the Foundation of the Contemporary Technological Revolution, has been continuously evolving from the early transistors to today’s advanced microchips. Historically dominated by powers such as the United States, the last decade has witnessed the rise of Asia, especially China, as a vital center for production and research, reshaping the geopolitical balance of the sector. Driven by the growing demand for electronic devices and digitization, the industry faces challenges such as the recent chip shortage, exacerbated by the COVID-19 pandemic. However, emerging technologies like tunnel gate transistors, graphene, and resistive memory promise to further revolutionize the field. This narrative review provides a comprehensive analysis of the evolution of semiconductors, highlighting technological innovations, current challenges, and geopolitical implications, with a special focus on the intersection between economy and technology.

Semiconductors in the Digital Age: Evolution, Challenges, and Geopolitical Implications

SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation

Aiming at the impact of Chiplet-to-Chiplet testing and the problem of insufficient number of chip ports after integration, the paper proposes a dynamically configurable Chiplet testing technology based on TAP controller architecture (TAP CA). The TAP CA includes TAP state machine controller module, instruction register module and data register module. The TAP state machine controller is used to control the instruction register, and then control and configure the corresponding data register through the instruction register. Finally, the data register is used to control the enable and disable operations of each Chiplet. When the Chiplet is enabled, the Chiplet enters the testing phase. Based on the IEEE 1687 standard, the TAP state machine inside TAP CA is used to realize built-in-self-test. Finally the data value of the configured data register is used to complete the output operation of chip. The above circuit is implemented based on TSMC 40nm process, and the area of TAP CA is only 12085.517 um^2. The ports for the memory testing of the Chiplet are only 5 JTAG ports. The built-in-self-test of all Chiplets can be implemented serially one by one based on TAP CS, and the Chiplet under testing is not affected by other Chiplets.

A Dynamically Configurable Chiplet Testing Technology Based on TAP Controller Architecture

As one of the breakthroughs in the semiconductor industry, chiplet-based design technology has changed the industry ecosystem by integrating multiple chiplets with different functions in the same package. In this paper, a chiplet-based system-on-chip (SoC) is introduced. This SoC can be widely applicable to different edge artificial intelligence (AI) applications. Compared to traditional systems with discrete components, it is much smaller, energy-efficient and supports shorter time to market.

Chiplet-based System-on-Chip for Edge Artificial Intelligence

Binarized Convolutional Neural Network (CNN) processor with mixed signal implementation has demonstrated ultra-low power operation capability in recent years. However low power advantage is valid at low signal to noise ratio (SNR) regimes, which limits the network size could be used thus sacrifice the computation capability. A mixed-signal binarized CNN processor, with group-based binarized CNN architecture is introduced. The SNR requirement of mixed signal processing is relaxed without sacrifices the network capability.

Low Power Mixed-Signal Binarized CNN Processor

For edge AI inference applications, one of the major challenges is to accomplish huge computation load using limited hardware resources and lowest power consumption. A groupwise architecture is proposed in this paper for accelerating neural network workload via hardware group parallelism and optimized processing element utilization. To achieve better efficiency and higher accuracy, the hardware is optimized by using customized groupwise networks and configurable processing element. The experiment results show that it could improve the accuracy by 2%, using CIFAR-10 dataset and MobileNet as the baseline model, at the expense of little growth in the number of parameters. Moreover, the groupwise topology also enhances hardware inference performance, in terms of frames per second, without additional hardware resource for running YOLO-Face network.

Hardware-oriented Groupwise Topology for CNN Accelerator

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Chiplet-based System-on-Chip for Edge Artificial Intelligence

Low Power Mixed-Signal Binarized CNN Processor

Hardware-oriented Groupwise Topology for CNN Accelerator