A serial port controller in an embedded disk drive controller is provided. The serial port controller includes a state machine that can access protocol information regarding plural devices operationally coupled to the serial port controller; a first register that can hold address information of the plural devices; and logic for enabling the plural devices for either a write or read request. The serial port controller also includes a second register for holding write data information for the plural devices; and a third register for holding read data information for the plural devices. The serial port controller reads programmed information regarding the plural device upon a client request; transmits the address of a device with whom communication is requested by the client; and transmits data to the plural devices, if the request by the client is to write data or collects data for a read request.

Method and system for supporting multiple external serial port devices using a serial port controller in embedded disk controllers

The operational bandwidth of a servo control circuit can be increased using a plurality of servo processors that handoff between them the responsibility for controlling head positioning in response to sequentially occurring servo patterns.

Servo processors that alternately control head positioning relative to sequential servo patterns

An embedded disk controller (“controller”) having a servo controller is provided. The controller also includes a servo controller interface with a speed matching module and a pipeline control module such that at least two processors share memory mapped registers without conflicts. The processors operate at different frequencies, while the servo-controller and the servo controller interface operate in same or different frequency domains. The pipeline control module resolves conflict between the first and second processor transaction. The speed matching module ensures communication without inserting wait states in a servo controller interface clock domain for write access to the servo controller and there is no read conflicts between the first and second processor. The controller also includes a hardware mechanism for indivisible register acess to the first or second processor. The hardware mechanisim includes a hard semaphore and/or soft semaphore.

Servo controller interface module for embedded disk controllers

A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.

Simulated error injection system in target device for testing host system

A method and system for generating interrupts in an embedded disk controller is provided. The method includes receiving vector values for an interrupt; determining if an interrupt request is pending; comparing the received vector value with a vector value of the pending interrupt; and replacing a previous vector value with the received vector value if the received vector value has higher priority. The system includes, at least one register for storing a trigger mode value which specifies whether an interrupt is edge triggered or level sensitive, and a vector address field that specifies a priority and address for an interrupt, and a mask value which masks an interrupt source. Also provided is a method for generating a fast interrupt. The method includes, receiving an input signal from a fast interrupt source; and generating a fast interrupt signal based on priority and a mask signal.

Interrupt controller for processing fast and regular interrupts

A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.

Method and system for embedded disk controllers

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Method and system for embedded disk controllers