The invention discloses a DMA data transmission system based on an embedded motion control board card and a transmission method of the DMA data transmission system, wherein a self-researched embedded motion controller is adopted The DMA data transmission system comprises an FPGA logical processing module, a DSP module and a motor control module, wherein the DMA function is embedded into the DSP module According to the DMA data transmission method, by means of cooperative work of an upper computer, an FPGA and a DSP and reasonable distribution of a time period and a program segment, batch data interaction between the upper computer and the motion control board card and batch data interaction between internal modules of the motion control board card are achieved, and therefore accurate control over a servo motor by the motion controller is achieved

DMA data transmission system based on embedded motion control board card and transmission method thereof

The invention discloses an EPA (Ethernet for Plant Automation) communication IP (Intellectual Property) core and a system on chip (SOC) based on an AMBA (Advanced Microcontroller Bus Architecture) bus structure. An EPA protocol stack is encapsulated into an IP hard core, and the IP core comprises an EPA module, an AHB (Advanced High-performance Bus) interface module, a DMAC (Direct Memory Access Controller) module, a data communication interface module and a register module. The EPA protocol stack is hooked on an AMBA bus, and constructs the SOC together with units such as a CPU (Central Processing Unit), an SRAM (Static Random Access Memory) and a FLASH. The EPA communication IP core and the system on chip have the beneficial effects that the technical advantages of an ARM (Advanced RISC Machine)+FPGA (Field Programmable Gate Array) platform are realized, and the defects of high cost, easiness in cracking a core technology and the like in the platform are successfully overcome; based on the implemented efficient interface-open SOC, a communication system based on EPA is more stable and reliable; and by adopting the IP core provided by the invention, an EPA communication function is realized, and a redundant function and an accurate clock synchronizing function are supported.

EPA (Ethernet for Plant Automation) communication IP (Intellectual Property) core and system on chip (SOC) based on AMBA (Advanced Microcontroller Bus Architecture) bus structure

The invention discloses a method and a device for extending a processor instruction set and relates to the technical field of communication. Under the prerequisites of not modifying a processor core, the processing speed of the processor is improved. The method comprises the following steps: a monitoring module identifies instructions by an on-chip bus and stores an extended instruction in the instructions to a local storage; after the processor core loads from a memory to the extended instruction through the on-chip bus, the processor core decodes the extended instruction to generate undefined instruction abnormality; after the processor core executes a current instruction, the processor core executes an abnormality processing procedure, and suspends to execute the instruction after the extended instruction; in addition, the monitoring module triggers an execution module corresponding to the extended instruction to execute the extended instruction; the monitoring module controls the processor core to exit from the abnormality processing procedure, so that continuous execution of the instruction after the extended instruction by the processor core is facilitated. The method and the device disclosed by the invention are suitable for an execution process of the extended instruction.

Method and device for extending processor instruction set

The invention discloses a method for controlling a servo motor by a secondary controller, the secondary controller and a system. The method comprises the steps that the secondary controller receives an instruction of an upper computer, and judges whether the instruction is a function instruction or a positioning instruction; if the instruction is the function instruction, the function instruction is executed and a response is given; if the instruction is the positioning instruction, the positioning instruction is analyzed, feedback data are calculated, and synchronous adjustment output is calculated in real time. Due to the fact that the secondary controller is used, the motor can be controlled more easily and flexibly, reference point returning and positioning are more accurate, dependency on a PLC is reduced, and cost is reduced; the method for controlling the servo motor by the secondary controller, the secondary controller and the system are suitable for long-distance drive, and the capacity of resisting disturbance is improved.

Method for controlling servo motor by secondary controller, secondary controller and system

The invention discloses a PLC program scheduler IP core based on an AMBA bus. The PLC program scheduler IP core includes an AHB interface module, a cycle task scheduling module, a timed task scheduling module and an interrupt task scheduling module, wherein the AHB interface includes a plurality of registers, a controller configures task information for the register and monitors task states of the register by the AMBA bus, the task information includes a program section number and a data section number, and the PLC program scheduler IP core based on the AMBA bus provides the program section number and the data section number to an executer for executing corresponding tasks; the cycle task scheduling module is connected with the AHB interface module for scheduling cycle tasks; the timed task scheduling module is connected with the AHB interface module and the cycle task scheduling module for scheduling timed tasks and pending the cycle task scheduling module; the interrupt task scheduling module is connected with the AHB interface module, the cycle task scheduling module and the timed task scheduling module for scheduling interrupt tasks, and pending the cycle task scheduling module and the timed task scheduling module.

PLC program scheduler IP core based on AMBA bus

A motion control on-chip system comprises an embedded processor core, a memory system, a DMA (Direct Memory Access) controller, a communication module IP (Internet Protocol) core, a motion control IP core and a plurality of peripheral interfaces, wherein the motion control IP core comprises an on-chip bus, an automatic instruction reading module, an automatic variable reading module, a register block, an interpolation control module, a single-axis control module, a speed control module, a pulse output module and an interruption processing module; the automatic instruction reading module of the motion control IP core autonomously reads a numeric control instruction and acquires an instruction parameter or variable from a register system through the on-chip bus, transmits relevant data of interpolation position to the interpolation control module and transmits the relevant data of speed control to the speed control module; when the instruction which can be immediately executed is read, corresponding actions are automatically started to execute according to current parameters; and pulses generated by the processing of interpolation control and speed control generate driving pulses with specified forms through the pulse output module.

Motion control on-chip system

The invention discloses an IP (intelligent property) core of a PLC (programmable logic controller) program performer. The intelligent core is hitched on an on-chip bus through a bus interface, and meanwhile, an MCU (microprogrammed control unit) and a storage are hitched on the on-chip bus. The IP core comprises a bus interface module, a program counting module, an instruction reading module, an addressing module, a data fetching module and a performing module. The bus interface module comprises a plurality of registers. The PLC program is an IL (intermediate language) program, and is stored in a 32bit fixed-length instruction set format. The IP core is hitched on the on-chip bus through the bus interface, receives control signals through the registers, reads IL instructions from the storage hitched on the on-chip bus and cooperates with the registers to execute the instructions through each module. The IP core can execute the PLC program efficiently at fast speed; and due to structural design of the IP core, performance affections and defects relative to hardware due to the fact that the PLC program execution only relies on the MCU are avoided, and the interface is open and easy to transplant.

IP (Intelligent property) core of PLC (programmable logic controller) program performer

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Motion control on-chip system

IP (Intelligent property) core of PLC (programmable logic controller) program performer