17 Papers
126 Citations
P. Muller is an academic researcher from École Polytechnique Fédérale de Lausanne. The author has contributed to research in topics: Jitter & Clock recovery. The author has an hindex of 7, co-authored 17 publications. Previous affiliations of P. Muller include École Normale Supérieure.
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Papers
High-speed Si resonant cavity enhanced photodetectors and arrays
TL;DR: In this paper, Emsley et al. proposed resonant cavity enhanced (RCE) photodetectors in compound semiconductors, operating at optical communication wavelengths ranging from 850 nm to 1550 nm.
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•Book
CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications
P. Muller,Yusuf Leblebici +1 more
- 08 Oct 2007
TL;DR: CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications provides the reader with the necessary background knowledge to fully understand the trade-offs in short-distance communication receiver design and presents the key issues to be addressed in the development of such receivers in CMOS technologies.
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A Power-Efficient Clock and Data Recovery Circuit in 0.18 $\mu{\hbox {m}}$ CMOS Technology for Multi-Channel Short-Haul Optical Data Communication
Armin Tajalli,P. Muller,Yusuf Leblebici +2 more
- 24 Sep 2007
TL;DR: This paper studies the specifications of gated-oscillator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems and proposes a top-down design methodology to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied.
Realization of high-efficiency 10 GHz bandwidth silicon photodetector arrays for fully integrated optical data communication interfaces
M.K. Emsley,O.I. Dosunmu,M.S. Unlu,P. Muller,Yusuf Leblebici +4 more
- 16 Sep 2003
TL;DR: In this paper, a commercially reproducible fabrication technique for producing high quantum efficiency photodiodes with up to 10 GHz bandwidth on double silicon-on-insulator (SOI) wafers is presented.
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Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
P. Muller,Armin Tajalli,Mojtaba Atarodi,Yusuf Leblebici +3 more
- 07 Mar 2005
TL;DR: This work presents a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators and Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing.