A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication. Additionally, a trellis sequence detector detects an estimated binary sequence from the synchronous sample values, wherein a state transition diagram of the trellis detector is configured according to the code constraints of the first and second channel codes. The estimated binary sequence output by the sequence detector is buffered in a data buffer to facilitate the error detection and correction process, and to allow for retroactive and split-segment symbol synchronization using multiple sync marks.

Disk storage system employing error detection and correction of channel coded data, interpolated timing recovery, and retroactive/split-segment symbol synchronization

In one embodiment of the invention, during add-compare-select computations, the output of the adders is guaranteed to be a positive value because the only time normalization logic subtracts a normalization amount is when all accumulators are greater than the normalization amount. As such, the detection of overflow is greatly simplified. Overflow in the add-compare-select unit may be indicated simply by the value of the most significant bit (“MSB”) (i.e., the sign bit) of the result. If the MSB of the result of the adder is set then, in one embodiment, the output of the adder gets forced the maximum possible value given the number of bits. For example, this value will be forced to 7h7f if the value is represented by 7-bits. That is to say, if an overflow is detected, then the accumulator is saturated to the maximum value.

Apparatus and method for saturating decoder values

A sampled amplitude read channel for use in disk storage systems (magnetic or optical) is disclosed comprising a simplified branch metric calculator for use in a trellis sequence detector. Instead of computing the traditional Euclidean branch metric as the squared difference between the actual signal sample and the expected signal sample of the target partial response, the present invention computes a simplified branch metric which is then saturated in order to reduce the number of bits required to calculate and store the branch metrics, thereby simplifying the branch metric calculators as well as reducing the add-compare-select (ACS) circuitry for each state in the trellis. Furthermore, the saturation technique of the present invention is substantially data independent meaning that the saturation threshold is essentially independent from the signal samples used to compute the branch metric.

Simplified branch metric for reducing the cost of a trellis sequence detector in a sampled amplitude read channel

Methods and apparatus are provided for measuring the performance of a read channel. A number of detection techniques, such as SOVA and maximum-a-posteriori (MAP) detectors, produce a bit decision and a corresponding reliability value associated with the bit decision. The reliability value associated with the bit decision may be expressed, for example, in the form of log likelihood ratios (LLRs). The reliability value can be monitored and used as a performance measure. The present invention provides a channel performance measure that generally correlates directly to the BER but can be collected in less time.

Method and Apparatus for Evaluating Performance of a Read Channel

An error correction system (1000) included in a utilization device (1002) operates upon a plurality of sectors (S) stored in a data buffer (1100) for performing write-from-host and read-from-device operations Overlapping and asynchronous operational steps are performed with respect to the plurality of sectors, the operational steps including sector transfer into buffer, sector correction, and sector transfer out of buffer The error correction system (1000) includes a plurality of subsystems which are supervised and sequenced by correction controller (1020) The subsystems include a CRC generation and checking subsystem (1030); an LBA subsystem (1040); an ECC/Syndrome Generator subsystem (1050); a header (ID) subsystem (1060); a correction subsystem (1070); and, a correction checker system (1075)

Error correction method and apparatus

In a typical Viterbi demodulator implemented using the add, compare, select (ACS) method, each state in the expected sample sequence model is associated with a hardware module to perform the functions of adding new branch error metrics to path error metrics, comparing path error metrics, and selecting the path having the lowest path error metric An ACS module may have two or more sequence-model states dynamically associated with it, such that at some times one sequence-model state is associated with it and at other times another sequence-model state is associated with it This reduces the number of ACS modules required and also reduces the size/complexity of the demodulator's path memories which must store one path for each ACS module Groups of sequence-model states may be chosen to share an ACS module without significant loss in performance as compared to the original, unreduced Viterbi demodulator

Method and apparatus for reduced-complexity viterbi-type sequence detectors

Practical Error Correction Design for Engineers

Apparatus and methods are disclosed for providing fast decoding of Reed-Solomon and related codes. Cases of one and two data symbol errors are decoded directly from the remainder using a large pre-computed table without calculating syndromes. Techniques for decoding cases of more than two errors are given where an optimized Chien search is used when more than four errors remain; when four or fewer errors remain, the Chien search is eliminated in favor of locating an error by direct solution of the error locator polynomial. The error locator and syndrome polynomials are adjusted after each error is found, and the error evaluator polynomial need not be computed.

Fast remainder decoding for a Reed-Solomon code

A filter for compensating discrete secondary pulse formations associated with a data stream of discrete main pulses produced from data read from magnetic media. The filter's impulse response comprises a center coefficient with side compensating coefficients for attenuating the secondary pulses when the input signal is convolved with the impulse response. The magnitude and delay of the compensation coefficients are programmable and are adaptively adjusted to optimize the impulse response for a given environment. In a traditional FIR embodiment, two delay lines are used to generate the two programmable delays between the center coefficient and side compensation coefficients. In the preferred embodiment, an IIR filter provides the two programmable delays using only one delay line thereby reducing the size and cost of the circuit. Also in the preferred embodiment, the data stream is interleaved into an even and odd data stream and processed in parallel by two filters in order to double the throughput. Further, the pre-cursor correcting portion of the filter can be disabled in order to avoid delaying the data stream while still canceling the post-cursor secondary pulses. The filter also comprises attenuation and adder means to match the coincident sample values in amplitude and add them to substantially eliminate the effect of the secondary pulses in the discrete data stream.

Filtering a read signal to attenuate secondary pulses caused by pole tips of a thin film magnetic read head

Signal processing circuitry receives input signals representing modulation encoded binary data signals. The signal processing circuitry contains a plurality of signal quality detectors which monitor a corresponding plurality of different characteristics of each received signal to determine whether or not the signal is of an adequate quality insofar as concerns the characteristic of the signal associated with each detector. Each detector generates a binary output signal representing a confidence level pointer associated with each such received signal. The pointer signals are stored in a buffer with received data signals. The contents of the buffer, which at this time contain the bytes of the received data record as well as the associated pointer bytes, are made available to a control module. Only the data and redundancy bytes of the record stored in the buffer are used by the control module if the data bytes are of sufficiently high quality so that any errors in the data bytes can be corrected using the redundancy bytes. If the received data bytes of the record are corrupted so that they cannot be corrected by the use of only the redundancy bytes, the control module reads the data buffer to receive the pointer bits of the record. The pointer bits specify with particularity which data bytes likely, contain errors. The control module uses the received pointer bits together with the redundancy bytes to correct the corrupted data bytes.

Error pointers for enhanced error correction

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