It was found that series-parallel-connected Josephson junctions exhibit synchronized switching. The structure used makes possible a Josephson device with an output voltage equal to a multiple of the gap voltage. As a result one of the structures becomes almost the same as a direct-coupled-logic gate. However, multiple junctions are required and circuit parameters in the gate must be optimized for synchronized switching. In experiments, the synchronized switching of all junctions connected in series and parallel were demonstrated. A high-voltage gate was constructed using synchronized switching and was applied to a cell driver in a Josephson memory circuit. The output voltage was four times the gap voltage, and a fast access of 590 ps was obtained. Experimental results are described for three applications: a memory cell driver, a regulator, and an interface circuit. >

Applications of synchronized switching in series-parallel-connected Josephson junctions

This paper reviews progress in superconductor electronics over the decade since the discovery of the high temperature oxide superconductors (HTS). Almost simultaneously with that discovery was the development of a new process for low temperature superconductor (LTS) devices based on the Nb/AlOx/Mb whole wafer tunnel junction. Both of these developments facilitated a strong growth in applications. We review first the applications based on thin films with no Josephson junctions. This is mostly using HTS, which permits more convenient cooling thus making applications mere commercially viable. With their need for only one or two Josephson junctions, SQUID magnetometers have succeeded to the market place using HTS materials. Finally, we review progress in the volt standard and digital circuits, both of which require large numbers of junctions and at present can only be realized with LTS materials.

Superconductor electronics, 1986-1996

A 4-kb Josephson nondestructive readout (NDRO) random access memory (RAM) has been developed. A process for fabricating the 580-ps 4-kb Josephson NDRO RAM is described that is based primarily on the use of Nb/AlO/sub x//Nb technology and state-of-the-art planarization. The process has evolved from a 1-kb Josephson NDRO RAM previously reported, with changes in memory cell structure, multilevel construction, layer planarization, and minimum design rules. Advanced memory cells with two stacked superconducting loops on which control lines are prepared are formed on ground plane insulation layers. Eight-stacked layers are formed from 200 approximately 300-nm-thick Nb films and 200-nm-thick SiO/sub 2/ films for planarized four-level interconnections including resistors. Planarization is achieved mainly by means of an undercut etching-mask-use lift-off planarization (ULOP) process. A 6-mm-square chip containing more than 25000 junctions whose minimum size is 3 mu m square and top level lines as small as 1.5 mu m in width and space have been successfully fabricated.

A fabrication process for a 580 ps 4 kbit Josephson non-destructive read-out RAM

Josephson semiconductor interface circuit

An experimental 4-bit Josephson processor that demonstrates the possibility of a Josephson computer system with a gigahertz clock is presented. Constructed from 2066 gates on a 5-mm*5-mm die, it implements an eight-instruction set to enable the basic operations of digital signal processing. The basic structure and operating principles of the Josephson device are reviewed, and the design of and operating results for the processor are presented. The focus is mainly on the circuit techniques required to realize a gigahertz clock in a Josephson processor. Circuit techniques to suppress the crosstalk from the AC power to the I/O lines and ways to improve the clock frequency are introduced. The problems remaining in the effort to enhance performance are discussed. >

A 4-bit, 250-MIPS processor using Josephson technology

A 4 b Josephson data processor chip

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A 4 b Josephson data processor chip