We present single- and dual-rail mixed pass-transistor logic (PTL) synthesis method based on genetic search and compared the results with their conventional static CMOS counterparts synthesized using a commercial logic synthesis tool in terms of area, delay, and power in an experimental 0.1- and 0.13-/spl mu/m CMOS technologies as well as a 0.13-/spl mu/m floating-body partially depleted silicon-on-insulator (PDSOI) process. The proposed synthesis method first performs a search for possible matches between a logic structure and a set of predefined PTL/static logic gates using binary decision diagrams (BDDs). The unique contribution of our approach is the use of a genetic algorithm to determine the best mixture of PTL and static cells based on area and power. Our experimental results demonstrate that both single- and dual-rail mixed PTL circuits synthesized using the proposed mixed PTL/CMOS synthesis method outperforms their static counterparts in delay and power in bulk CMOS as well as silicon-on-insulator (SOI) CMOS technologies. The average power of single- and dual-rail mixed PTL/Static ISCAS'85 benchmark circuits using the proposed method in the 0.1-/spl mu/m bulk CMOS process are 73% and 50% better than their static counterparts with performance gains of 5% and 10%, respectively.

Synthesis of single/dual-rail mixed PTL/static logic for low-power applications

In battery-operated portable or implantable digital devices, where battery life needs to be maximized, it is necessary to minimize not only power consumption but also energy dissipation. Typical energy optimization measures include voltage reduction and operating at the slowest possible speed. We employ additional methods, including hybrid asynchronous dynamic design to enable operating over a wide range of battery voltage, aggregating large combinational logic blocks, and transistor sizing and reordering. We demonstrate the methods on simple adders, and discuss extension to other circuits. Three novel adders are proposed and analyzed: a 2-bit pass transistor logic (PTL) adder and two dynamic 2-bit adders. Circuit simulations on a 0.18-mum process at low voltage show that leakage energy is below 1%. The proposed adders achieve up to 40% energy savings relative to previously published results, while also operating faster

/pdf/minimal-energy-asynchronous-dynamic-adders-nt5eixdguu.pdf

Minimal Energy Asynchronous Dynamic Adders

Lowering power in an experimental RISC processor

In the present paper we have designed a 16-bit adder circuits with basic pass transistor circuit approach and different topology for implementation The proposed multiplexing control input techniques of the adder circuits are developed by the carry save adder (CSA) technique The different logic cells, used for various pass gates circuit design styles are evaluated in terms of area, propagation delay, power dissipation and propagation delay product The design styles are compared by performing detailed transistor-level simulations on a benchmark circuit (CSA adder) using DSCH3 and Microwind3 We have analysed the results in a statistical way We have compared our results with the various published results of adder circuits We found that the speed of the our proposed circuit is enhanced and power consumption as well as the area has reduced tremendously due to multiplexing control input technique Comparing the simulated results with other pass logic designs, it was observed that in all existing logic CPL is a promising candidate for future logic design

Statistical analysis of Power Delay Estimation in adder circuit using non-clocked pass gate families

In this paper, we design the best fit driver for power transistors of the synchronous buck PWM converter for turning on and off and generating the desired output. To find the best fit driver, four circuits were implemented using 0.18 mum CMOS technology, and cadence was used to simulate and verify the functionality of these circuits. The design criteria of these drivers depend on power dissipation, delay, and physical size. The best design consists of the novel buck driver with the synchronous DC-DC buck converter. The DC input voltage of this design was 1.2 V, and the DC output voltage of this design was 1.0 V along with output current was 120 mA. The maximum frequency range of this design was up to 100 MHz. The total size of this converter was around 154 mm2 plus the area of the inductor and capacitor. The designed converter achieved the required specification, and its efficiency was up to 94.9%

Implementation of novel low-power driver for integrated buck converter

We show that SPL (single-ended pass transistor logic) is a promising logic style for low power design especially for arithmetic functions. SPL uses mainly NMOS transistors, the layout is compact, simple and regular (only 10 library cells required) but synthesis is more difficult. We compare SPL (using single and split supply voltages) with CPL and CMOS circuits for standard elements using a commercial 0.35 /spl mu/m process. SPL is better by up to 3x in power and 2x in area. We also discuss the limitations and difficulties of SPL and possible solutions.

http://ieeexplore.ieee.org/iel5/6676/18015/00832353.pdf

Single-ended pass transistor logic for low-power design

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Single-ended pass transistor logic for low-power design