A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Method and system for storage of data in non-volatile media

Transport stream (TS) packets containing sections of IP datagrams for an application level process are received and correct ones of said sections are stored into an MPE-FEC frame buffer of a receiver. Stored ones of said sections are reorganized within the frame buffer so as to leave appropriate positions, marked for erasure, within the frame buffer available for corrected data. Data bytes stored at the appropriate positions may be corrected using Reed-Solomon parity data stored in the frame buffer and then subsequently written back thereto.

Error resilience methods for multi-protocol encapsulation forward error correction implementations

A data communications architecture employing serializers and deserializers that reduces data communications latency. In an illustrative implementation, the data communications architecture communicates data across communications links. The architecture maintains various mechanisms to promote data communications speed and to avoid communication link down time. These mechanisms perform the functions including but not limited to handling uncertain data arrival times, detecting single bit and multi-bit errors, handling communications link failures, addressing failed link training, identifying and marking data as corrupt, and identifying and processing successful data transactions across the communications link.

Failed link training

A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Mesosynchronous data bus apparatus and method of data transmission

An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Skew management in an interconnection system

A microchip configured to reliably transmit data is provided. The microchip includes a memory region and a selection module configured to select a portion of the data from the memory region. An error checking module configured to calculate a value derived from the selected portion of the data is provided. A pointer region including a plurality of object pointers is included. One of the object pointers is associated with an address of the portion of the data. The object pointer associated with the address is configured to receive a signal indicating an error associated with the transmission of the data. A scheduler module in communication with each of the plurality of object pointers is provided. The scheduler module is configured to schedule re-transmission of the selected portion of the data. A system and a method for reliably transmitting data between microchips are also provided.

Switch level reliable transmission

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Switch level reliable transmission