A voltage regulator circuit includes a transistor and a capacitor. The transistor includes a gate, a source, and a drain, a first signal is inputted to one of the source and the drain, a second signal which is a clock signal is inputted to the gate, an oxide semiconductor layer is used for a channel formation layer, and an off-state current is less than or equal to 10 aA/μm. The capacitor includes a first electrode and a second electrode, the first electrode is electrically connected to the other of the source and the drain of the transistor, and a high power source voltage and a low power source voltage are alternately applied to the second electrode.

Voltage regulator circuit

With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost.

Semiconductor Device and Electronic Apparatus Having the Same

The invention provides for the efficient use a substrate region in a liquid crystal device with built-in driving circuits which simultaneously drives a plurality of data lines, etc. One of substrates used for the liquid crystal device may include a plurality of latch circuits for sequentially outputting transfer signals, buffer circuits for outputting sampling-control signals via signal lines by performing wave shaping on the transfer signals input via wires, and sampling switches for sampling, in accordance with the sampling-control signals, video signals supplied to video-signal lines, and for supplying the sampled signals to the corresponding data lines. The buffer circuits each comprise inverters connected in series in three stages in a direction in which the data lines extend, and the inverter in each stage comprise seven inverters connected in parallel in a direction intersecting the extended direction of the data lines.

Driving circuit for electrooptical device, electrooptical device, and electronic apparatus

In a shift register block according to the present invention, a plurality of flip-flops F/F( 1 ), F/F( 2 ), . . . F/F(n) constitute a shift register SR, and each adjacent ones of these flip-flops are therebetween having a corresponding one of waveform processing circuits WR( 1 ) through WR(n), so that the shift register SR and the waveform processing circuits WR( 1 ) and WR(n) are linearly aligned. With such an arrangement, it is possible to reduce area occupied by a signal line driving circuit including the sift register block, thereby narrowing the frame area of a display device.

Shift register block, and data signal line driving circuit and display device using the same

PROBLEM TO BE SOLVED: To control a voltage of a capacitor by which a final step-up voltage can be obtained to a reference voltage level during non-step-up operation, and to control each step-up control signal during the non-step-up operation so as to make the signal reach a power source voltage level or the reference voltage level. SOLUTION: The step-up voltage output node of a charge-pump circuit 150 is connected to a connection terminal of a capacitor via a first switch, and a second switch is provided in parallel to the capacitor. The first and second switches are controlled so as to be turned off and on, respectively, during the non-step-up operation. Furthermore, an electric passage is formed between a power source line and the step-up voltage output node so that a power source voltage can be supplied to the node. COPYRIGHT: (C)2007,JPO&INPIT

Step-up circuit

PROBLEM TO BE SOLVED: To suppress the dispersion of the output voltage of a DC-DC converting circuit caused by the dispersion of the threshold voltage of a thin film transistor. SOLUTION: This DC-DC converting circuit compares the inter-terminal voltage of the third capacitor C3 being the output voltage of itself and the reference voltage, and switches on or switches off a switch element P6 connected between a DC-DC converter 1 and the third capacitor C3, based on this comparison result. For example, in case of step-up type, when the inter-terminal voltage of the third capacitor C3 becomes larger than the reference voltage, it switches off the switch element P6 so that it may not charge the third capacitor C3. On the other hand, when the inter-terminal voltage of the third capacitor C3 becomes smaller than the reference voltage, it switches on the switching element P6 so as to charge the third capacitor C3. Hereby, it is arranged so that the output voltage GVDD may be constant. COPYRIGHT: (C)2006,JPO&NCIPI

Dc-dc converting circuit

PROBLEM TO BE SOLVED: To provide a thin-film transistor circuit capable of reducing a temperature rise SOLUTION: Thin-film transistors Q1, Q2 are turned on in an electrical charge period, and thin-film transistors Q3, Q4 are turned on in an electrical discharge period In a word, there are alternately arranged a thin-film transistor which is turned on in the electrical charge period, and a thin-film transistor which is turned on in the electrical discharge period COPYRIGHT: (C)2007,JPO&INPIT

Thin film transistor circuit

PROBLEM TO BE SOLVED: To secure a sufficient picture signal band without increasing the occupying area of a signal conductor driving circuit by distributing a timing signal to a buffer circuit and a distributing switch after a control line and picture signal bus wiring cross each other or without crossing each other at all. SOLUTION: An output signal is inputted in the same timing to analog switch group 14 from a timing signal generating circuit 11 through a buffer circuit group 12 in the same number rows as this. An output signal conductor 17 distributes a timing signal in response to the row number of a buffer circuit 12 after crossing only in the vicinity of a cross point 113 with bus wiring 13. Output lines of the buffer circuit 12 are control wiring 18 to drive gates 110, and these are electrically connected to each other, and uniformly transmit the timing signal to the analog switches 110. The picture signal bus wiring 13 is connected to respective elements of an analog switch 14, and since the output lines 111 are connected to a signal conductor 120, a parasitic capacity load of the picture signal bus wiring 13 is reduced, and reduction in a band characteristic is prevented. COPYRIGHT: (C)1998,JPO

Driving circuit integrated display device

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Dc-dc converting circuit

Thin film transistor circuit

Driving circuit integrated display device