We present a novel method, that we call EVENODD, for tolerating up to two disk failures in RAID architectures. EVENODD employs the addition of only two redundant disks and consists of simple exclusive-OR computations. This redundant storage is optimal, in the sense that two failed disks cannot be retrieved with less than two redundant disks. A major advantage of EVENODD is that it only requires parity hardware, which is typically present in standard RAID-5 controllers. Hence, EVENODD can be implemented on standard RAID-5 controllers without any hardware changes. The most commonly used scheme that employes optimal redundant storage (i.e., two extra disks) is based on Reed-Solomon (RS) error-correcting codes. This scheme requires computation over finite fields and results in a more complex implementation. For example, we show that the complexity of implementing EVENODD in a disk array with 15 disks is about 50% of the one required when using the RS scheme. The new scheme is not limited to RAID architectures: it can be used in any system requiring large symbols and relatively short codes, for instance, in multitrack magnetic recording. To this end, we also present a decoding algorithm for one column (track) in error. >

/pdf/evenodd-an-efficient-scheme-for-tolerating-double-disk-bdrj6a96kf.pdf

EVENODD: an efficient scheme for tolerating double disk failures in RAID architectures

We present a new class of MDS (maximum distance separable) array codes of size n/spl times/n (n a prime number) called X-code. The X-codes are of minimum column distance 3, namely, they can correct either one column error or two column erasures. The key novelty in X-code is that it has a simple geometrical construction which achieves encoding/update optimal complexity, i.e., a change of any single information bit affects exactly two parity bits. The key idea in our constructions is that all parity symbols are placed in rows rather than columns.

/pdf/x-code-mds-array-codes-with-optimal-encoding-4s1vh4gbq8.pdf

X-code: MDS array codes with optimal encoding

Proper data placement schemes based on erasure correcting codes are one of the most important components for a highly available data storage system. For such schemes, low decoding complexity for correcting (or recovering) storage node failures is essential for practical systems. In this paper, we describe a new coding scheme, which we call the STAR code, for correcting triple storage node failures (erasures). The STAR code is an extension of the double-erasure-correcting EVENODD code and a modification of the generalized triple-erasure-correcting EVENODD code. The STAR code is an Maximum Distance Separable (MDS) code and thus is optimal in terms of node failure recovery capability for a given data redundancy. We provide detailed STAR code decoding algorithms for correcting various triple node failures. We show that the decoding complexity of the STAR code is much lower than those of existing comparable codes; thus, the STAR code is practically very meaningful for storage systems that need higher reliability.

/pdf/star-an-efficient-coding-scheme-for-correcting-triple-54ybrkfrbt.pdf

STAR : An Efficient Coding Scheme for Correcting Triple Storage Node Failures

A method for operating a memory (28) that includes a plurality of analog memory cells (32) includes storing data in the memory by writing first storage values to the cells. Second storage values are read from the cells, and a Cumulative Distribution Function (CDF) of the second storage values is estimated. The estimated CDF is processed so as to compute one or more thresholds. A memory access operation is performed on the cells using the one or more thresholds.

Adaptive Estimation of Memory Cell Read Thresholds

A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

Reading memory cells using multiple thresholds

In this talk we investigate a number of on-chip coding techniques for the protection of Random Access Memories which use multi-level as opposed to binary storage cells. The motivation for such RAM cells is of course the storage 
of several bits per cell as opposed to one bit per cell [l]. 
Since the typical number of levels which a multi-level RAM can handle is 16 (the cell being based on a standard DRAM 
cell which has varying amounts of voltage stored on 
it) there are four bits recorded into each cell [2]. The disadvantage of multi-level RAMs is that they are much 
more prone to errors, and so on-chip ECC is essential for reliable operation. There are essentially three reasons for error control coding in multi-level RAMs: To 
correct soft errors, to correct hard errors, and to 
correct read errors. The source of these errors is, 
respectively, alpha particle radiation, hardware faults, and 
data level ambiguities. On-chip error correction can be 
used to increase the mean life before failure for all three types of errors. Coding schemes can be both bitwise and 
cellwise. Bitwise schemes include simple parity checks and SEC-DED codes, either by themselves or as product codes 
[3]. Data organization should allow for burst error correction, since alpha particles can wipe out all 
four bits in a single cell, and for dense memory chips, 
data in surrounding cells as well. This latter effect becomes more serious as feature sizes are scaled, and 
a single alpha particle hit affects many adjacent cells. Burst codes such as those in [4] can be used to correct for 
these errors. Bitwise coding schemes are more efficient 
in correcting read errors, since they can correct single bit 
errors and allow the remaining error correction power to be 
used elsewhere. Read errors essentially affect one bit 
only, since the use of Grey codes for encoding the bits 
into the memory cells ensures that at most one bit is flipped with each successive change in level. Cellwise schemes include Reed-Solomon codes, hexadecimal 
codes, and product codes. However, simple encoding and decoding algorithms are necessary, since excessive space taken by powerful but complex encoding/decoding circuits can 
be offset by having more parity cells and using simpler 
codes. These coding techniques are more useful for correcting hard and soft errors which affect the entire cell. They tend to be more complex, and they are not as 
efficient in correcting read errors as the bitwise codes. 
In the talk we will investigate the suitability and 
performance of various multi-level RAM coding schemes, 
such as row-column codes, burst codes, hexadecimal codes, Reed-Solomon codes, concatenated codes, and some new majority-logic decodable codes. In particular we investigate their tolerance to soft errors, and to feature size scaling.

/pdf/on-chip-ecc-for-multi-level-random-access-memories-3c531w6blj.pdf

On-Chip ECC for Multi-Level Random Access Memories

The mean lifetimes are studied of semiconductor memories that have been encoded with an on-chip single error-correcting code along each row of memory cells. Specifically, the effects of single-cell soft errors and various hardware failures (single-cell, row, column, row-column, and entire chip) in the presence of soft-error scrubbing are examined. An expression is presented for computing the mean time to failure of such memories in the presence of these types of errors using the Poisson approximation; the expression has been confirmed experimentally to accurately model the mean time to failure of memories protected by single error-correcting codes. These analyses will enable the system designer to accurately assess the improvement in mean time to failure (MTTF) achieved by the use of error-control coding. >

/pdf/the-reliability-of-semiconductor-ram-memories-with-on-chip-1an0yrda82.pdf

The reliability of semiconductor RAM memories with on-chip error-correction coding

A 2-kb CMOS static RAM with on-chip error-correction capability (ECCRAM chip) is described. The linear sum code (LSC)-based ECCRAM is capable of correcting error at any addressed bit as long as there are no more than two errors in the 17 b (the logical row and column) associated with that addressed bit. Test results show that significantly larger error-recovery capability is present in the ECCRAM chip compared to memory chips without error correction. The ECCRAM chip has been fabricated in a double-metal scalable CMOS process with a 3- mu m feature size. >

/pdf/a-static-ram-chip-with-on-chip-error-correction-3dkjwzytys.pdf

A static RAM chip with on-chip error correction

Array codes composed of row and column parities with a diagonally cyclic readout order are capable of correcting 
a single burst error along one diagonal. A new equation which defines permissible array sizes is presented. These codes have an optimal size which is shown to be a number theoretic problem. In addition, correction of approximate errors is presented; this can be generalized for many classes of error correcting codes.

/pdf/single-phased-burst-error-correcting-array-codes-2p82m6a33m.pdf

Single Phased Burst Error Correcting Array Codes

In this paper we study various improvements to a locally 
adaptive vector quantization (LAVQ) algorithm. The 
effects of including bit stripping, index compression, and filtering techniques will be discussed. Software implementation and comparisons with non-adaptive vector 
quantization algorithms will be studied.

/pdf/locally-adaptive-vector-quantization-for-image-compression-1xrofi3onr.pdf

Locally Adaptive Vector Quantization For Image Compression

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