The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Nowadays, fan-out package is regarded as one of the latest and most potential technologies because it possesses lower cost, thinner profile, and better electrical performance and thermal performance. However, thermally induced warpage in the molding process is a critical issue due to the larger wafer or panel size, the shrinkage of epoxy mold compound (EMC) during the curing stage, and the mismatch of coefficient of thermal expansion (CTE) among the constituent materials during the cooling stage, which needs to be controlled effectively for successful subsequent process of the fan-out package. In this paper, a novel $320 \times 320$ -mm2 panel-level fan-out package based on “Die Last” process is developed. A coreless substrate with redistribution layer is fabricated and bonded onto a low-CTE and high-glass-transition-temperature (Tg) FR4 carrier through thermal release film. The thermally induced warpage issue in the molding process is investigated. A warpage simulation method is presented and verified by Shadow Moire experiment. The error between the simulation and experimental results is about 4.8%. For the warpage optimization analysis, the effect of geometry structure on the warpage is first investigated by the design of simulation approach. Full factor experiment is conducted, and Minitab statistical software is utilized to analyze the effect of the geometry structure on warpage. It is found that decreasing die thickness and molding thicker EMC can effectively decrease the warpage. Then, the effects of molding temperature and in-plane CTE of FR4 on warpage are studied, respectively. When molding temperature is 120 °C and in-plane CTE of FR4 decreases to 10.5 ppm/°C, the thermally induced warpage in the molding process is only about 0.31 mm, thus subsequent process of fan-out package can be conducted successfully.

Experimental Verification and Optimization Analysis of Warpage for Panel-Level Fan-Out Package

To meet the requirements of low cost, thin vehicles, and multiple functions, the fan-out panel-level packaging (FO-PLP) is introduced to be one of the next-generation packaging technologies. However, the warpage issue of FO-PLP remains a critical concern during temperature cycling manufacturing processes. The utilization of finite-element analysis (FEA) to estimate the warpage of FO-PLP and to address the major mechanism of warp-induced failure is therefore crucial. Given that an increase in the structural complexity of packaging follows the advancement in technological development, the effect of redistribution layer (RDL) on packaging warp considered in FEA becomes greatly difficult. The complicated RDL might cause computational bottlenecks. For this reason, several equivalent material approaches composed of composite theory and simulation-based material testing approach are proposed and compared with resolve the abovementioned problem. The gravity effect is considered in the present process-oriented FEA to acquire accurate warpage. To perform the foregoing FEA, identifying how to determine the equivalent reference temperature at each step of manufacturing process is the key. In this article, three methods, namely, zero deformation approach, force equilibrium approach, and modified Timoshenko bimaterial approach, are proposed. To validate these methods, a comparison of warpage between the experimental measurement and simulation is conducted. The analytic results demonstrate that the modified Timoshenko approach has the best ability to evaluate the warpage of RDL-first FO-PLP among them due to the feasible assumption for the actual mechanical behavior of warpage. With regard to the extraction of equivalent material, the results indicate that the simulation-based material testing approach is more suitable to obtain the equivalent RDL. The estimated warpage has only a 0.9% deviation between the simulation and experiment when the modified Timoshenko bimaterial approach combined with the simulation-based material testing approach is adopted. Consequently, the RDL-induced warpage in FO-PLP can be accurately estimated through the presented simulation methodology.

Comparison of Mechanical Modeling to Warpage Estimation of RDL-First Fan-Out Panel-Level Packaging

The through-silicon via (TSV) technology is widely used in 3-D integrated circuit (3-D IC) devices. However, the TSV could cause great thermal stress due to the mismatch of the thermal expansion between different materials, which affects the performance of the 3-D IC. In this work, a finite element model of the 3-D IC device with both internal pin-fin microchannels and all-copper interconnection is established. A substructure model is further developed and validated against the results obtained from the full model. Then, the thermal–mechanical performances of the TSV structure under thermal cycling loads are investigated based on the substructure model. The results show that the maximum stress locates at the edge of the interface between TSV_copper and memory, and the deformation on the TSV_copper–memory interface is dominated by shearing, which may cause the debonding of the interface. Moreover, the influences of the TSV structure parameters on the maximum thermal stress and TSV_copper’s electrical resistance are analyzed. Then, the TSV structure is further optimized to reduce the stress and improve the electrical conductivity. Compared with the original design, the maximum von Mises stress and TSV_copper resistance of the optimized structure can be reduced by 18.4% and 40.6%, respectively.

Thermal–Mechanical Performance Analysis and Structure Optimization of the TSV in 3-D IC

The multi-chip module assembled with a composite layer of thin film on top of organic substrate is presented in this paper. This is a new-arising assembly technology with equivalent electrical performance of 2.5D package but much simplified supply-chain processes. We name this package as 2.1D package which converts the silicon interposer on the substrate. In this paper, the implementation of 2.1D technology on the monolithic, daisy-chain test vehicle is described. We employed thermal compression bonding (TCB) to mount two large dies with minimum 40 ?m-pitch micro bumps onto 45 x 45 mm organic substrate using 2/2 µm line width/space (L/S). Thermally induced misalignment, substrate warpage and the ELK (Extreme Low-K) stress during micro bumps joining with micro pads on substrate were evaluated. The mechanism of micro bump misalignment during solder formation has been experimentally and numerical validated by TCB and conventional mass reflow (MR) process. Finite element analyses were conducted to understand the 2.1D package warpage and stress behaviors, and hence defined better materials and process parameters. Simulation results showed that micro bump joining by TCB has 45% misalignment improvement as compared to MR process. In stress simulation results, the ELK layer stress of micro bump using TCB has a 59% reduction with reference to MR. In addition, the warpage behavior of fine-line organic substrate and 2.1D full package were measured using conventional shadow moire system. Results showed that the warpage variation of thin-film coated substrates was very stable within micro pads area that has less than 10 µm differences under high temperature period (120~260 °C). However, the package moire results showed that the thermally attaching of stiffener ring could significantly affect the global package warpage based on moire contours and warpage distributions. The reliability of this developed 2.1D, multi-chip test vehicle using TCB assembling processes was validated as well. This package passed MSL4 preconditioning and 1000 thermal cycles using G-conditions (-40~125 °C).

Analysis of Warpage and Stress Behavior in a Fine Pitch Multi-Chip Interconnection with Ultrafine-Line Organic Substrate (2.1D)

In flip-chip packages, the coefficient of thermal expansion (CTE) mismatch between the chip and the substrate is the root cause for reliability issues such as excessive warpage, low- $k$ dielectric layer cracking, solder mask cracking, and bump cracking. The first and foremost thing in designing a flip-chip package is to meet the warpage specification. This paper proposes a capped-die flip-chip package to control the warpage as well as to reduce the stress in solder bumps. In the capped-die flip-chip package, a metal cap tightly covers and bonds with the die through an adhesive material, leading to a capped die with a higher effective CTE. By adjusting the thickness of the metal cap, the effective CTE of the capped die may match with that of the substrate, theoretically achieving zero warpage or warpage free. Guided by finite-element analysis, a $45\times 45$ -mm2 size of capped-die flip-chip package was manufactured, and a copper die cap with 0.4 mm thickness is selected to verify this concept. Shadow Moire test data showed that in the temperature range from 25 °C to 260 °C, the warpage curve of the capped-die package is almost flat and close to zero, confirming the capped-die concept. Furthermore, finite-element modeling was used to investigate the stress in bump, as well as the thermal performance of the capped-die flip-chip packages. It is found that thermal performance of the capped-die package can be good enough for high-power applications. The bump stress of the capped-die package is about 50% lower compared to the lidded package. The applications of the capped-die package design in coreless substrate packages are also discussed in this paper.

Finite-Element Analysis and Experimental Test for a Capped-Die Flip-Chip Package Design

Coefficient of thermal expansion (CTE) mismatch between chip and substrate is the root cause for reliability issues in flip chip packages, such as excessive warpage, low-k dielectric layer cracking, solder mask cracking, and bump cracking. The first and foremost thing in designing a flip chip package is to control excessive warpage to meet the warpage specification. In this paper, a capped-die flip chip package is proposed to control the warpage as well as to reduce the stress. In the capped-die flip chip package, a metal cap tightly covers and bonds with the die through an adhesive material. As a result, the capped-die has a higher effective CTE. By adjusting the thickness of metal cap, the effective CTE of the capped-die can matches with the CTE of substrate, theoretically achieving zero-warpage or warpage-free. To verify the capped-die concept for zero-warpage control, a 45mm×45mm size of capped-die flip chip package is designed and manufactured based on the guidance from finite element modeling, where a copper die-cap with 0.4mm thickness is selected. Then, Shadow Moire test is performed to measure the warpage as function of temperature from 25°C to 260°C. Experimental data show that in the temperature range, the warpage curve of the capped-die package is almost flat and close to zero, verifying the capped-die concept.

/pdf/achieving-warpage-free-packaging-a-capped-die-flip-chip-3qd3qcw43u.pdf

Achieving warpage-free packaging: A capped-die flip chip package design

Handheld and mobile application processors are under high pressure of performance, form factor and cost. In this paper, we reviewed one high performance, low profile, low cost package on package (PoP) developed for NVIDIA's TK1 SOC. Detailed package special structure and unique substrate manufacture process flow are presented in this paper to explain how this package meets performance, form factor and cost challenges. This package also shows very robust reliability. No special toolings were needed for this package's handling, assembly process and surface mount process. Existing assembly line and SMT line were used for package manufacture and SMT. High layer count PoP products (8L and 7L coreless) have been designed with this technology. This product was successfully built and used in high performance handheld applications in high volume production Patents are in filling process.

Low cost high performance bare die PoP with embedded trace coreless technology and “coreless cored” build up substrate manufacture process

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Finite-Element Analysis and Experimental Test for a Capped-Die Flip-Chip Package Design

Achieving warpage-free packaging: A capped-die flip chip package design

Low cost high performance bare die PoP with embedded trace coreless technology and “coreless cored” build up substrate manufacture process