A magnetoresistive element according to an embodiment includes: a first ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a second ferromagnetic layer having an axis of easy magnetization in a direction perpendicular to a film plane; a nonmagnetic layer placed between the first ferromagnetic layer and the second ferromagnetic layer; a first interfacial magnetic layer placed between the first ferromagnetic layer and the nonmagnetic layer; and a second interfacial magnetic layer placed between the second ferromagnetic layer and the nonmagnetic layer The first interfacial magnetic layer includes a first interfacial magnetic film, a second interfacial magnetic film placed between the first interfacial magnetic film and the nonmagnetic layer and having a different composition from that of the first interfacial magnetic film, and a first nonmagnetic film placed between the first interfacial magnetic film and the second interfacial magnetic film

Magnetoresistive element and magnetic memory

An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost A method for manufacturing a semiconductor device includes the following steps: forming a semiconductor film; irradiating a laser beam by passing the laser beam through a photomask including a shield for shielding the laser beam; subliming a region which has been irradiated with the laser beam through a region in which the shield is not formed in the photomask in the semiconductor film; forming an island-shaped semiconductor film in such a way that a region which is not irradiated with the laser beam is not sublimed because it is a region in which the shield is formed in the photomask; forming a first electrode which is one of a source electrode and a drain electrode and a second electrode which is the other one of the source electrode and the drain electrode; forming a gate insulating film; and forming a gate electrode over the gate insulating film

Method for Manufacturing Semiconductor Device

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

https://ir.nctu.edu.tw/bitstream/11536/21381/1/000316677900001.pdf

Growth, dielectric properties, and memory device applications of ZrO2 thin films

The degradation of ferroelectric (FE) properties of atomic layer deposited Hf0.5Zr0.5O2 films with increasing thickness was mitigated by inserting 1 nm-thick Al2O3 interlayer at middle position of the thickness of the FE film. The large Pr of 10 μC/cm2, which is 11 times larger than that of single layer Hf0.5Zr0.5O2 film with equivalent thickness, was achieved from the films as thick as 40 nm. The Al2O3 interlayer could interrupt the continual growth of Hf0.5Zr0.5O2 films, and the resulting decrease of grain size prevented the formation of non-ferroelectric monoclinic phase. The Al2O3 interlayer also largely decreased the leakage current of the Hf0.5Zr0.5O2 films.

Grain size engineering for ferroelectric Hf0.5Zr0.5O2 films by an insertion of Al2O3 interlayer

According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.

Magnetoresistive element and method of manufacturing the same

New ZrO2/Al2O3/ZrO2 (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO2 and amorphous phase Al2O3 in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 A and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.

New TIT capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60 nm and below DRAMs

New ZrO2/Al2O3/ZrO2 (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO2 and amorphous phase Al2O3 in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 Aring and low leakage current density of 0.35fA/cell, which meet leakage current criteria of 0.5fA/cell for mass production. ZAZ TIT capacitor showed smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550degC anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range

New TIT Capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60nm and below DRAMs

A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.

Capacitor forming method

A phase change memory device is provided that includes a switching device, a bottom electrode contact in contact with the switching device and a porous spacer formed on the bottom electrode contact.

Phase-change memory device and fabrication method thereof

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