A testing method of electronic devices, each of which includes a central processing unit (CPU) for running an operating system (OS), includes the following steps when testing one of the electronic devices. The specification of the CPU of the electronic device and the version of the OS run on the CPU are identified. A test script of the electronic device is searched from a script lookup table according to the specification of the CPU and the version of the OS. The script lookup table records a variety of test scripts related to the specification of a variety of CPUs of a variety of electronic devices in combination with the version of a variety of operating systems. The found test script is provided to a testing module. The electronic device is tested by the testing module according to the found test script.

Testing method of electronic devices

The invention discloses a method for checking the quality of server main board memory signals through a BMC, and relates to the field of main board management. The method includes the steps that a BIOS is modified, memory signal quality data tested by an MRC code in the BIOS starting process is stored into an FRU EEPROM of a main board, after the BIOS is started, the BMC is informed of reading the memory signal quality data tested by the MRC code in the EEPROM and storing the memory signal quality data, and then the data is displayed visually through a BMC management interface. The test data of multiple adjacent memory signals can be checked in the BMC management interface so as to help people to know about the current memory signal condition, problems related to a memory are located, and development personnel are helped to check the quality of the memory signals and related problems caused by locating the memory.

Method for checking quality of server main board memory signals through BMC

The invention provides a CPU testing method and device and an electronic device. In the invention, decay commands in SETWP testing and the command execution time corresponding to each command after the decay command can be automatically configured, thereby realizing correct SETWP testing of the CPU and obtaining test results. According to the embodiment of the invention, the parameter value of thedelay corresponding to each command does not need to be adjusted manually.

CPU testing method and device and electronic device

The present invention provides a CPU testing method and apparatus, and an electronic device. In the present invention, a decay command in SETWP testing and the command execution time corresponding to each command subsequent to the decay command can be automatically configured, thereby implementing correct SETWP testing of a CPU and obtaining a test result. According to the embodiments of the present invention, there is no need to manually adjust the parameter value of the delay corresponding to each command.

Cpu testing method and apparatus, and electronic device

The invention discloses VR power supply debugging equipment and method. According to the implementation process, first, a CPLD is configured, the CPLD is connected with a serial port, an EEPROM, a VR power supply chip and a CPU, then an SVID master module, an SVID slave module and a serial port module meeting an SVID protocol are set up in the CPLD, parameters of the SVID master module or the SVID slave module are configured through the serial port module, the configured parameters are stored in the EEPROM, and finally the SVID master module simulates the CPU to send an instruction or the SVID slave module simulates the VR power supply chip to complete debugging on a VR power supply. Compared with the prior art, the VR power supply debugging equipment and method are suitable for debugging of a mainboard with a VR power module of an X86 platform of Intel, debugging cost is effectively lowered, debugging efficiency is high, problem positioning is accurate and fast, practicability is high, the application range is wide, and popularization is easy.

VR power supply debugging equipment and method

The invention discloses an SVID based memory voltage level bias testing method. When an MRC operates in a memory initialization phase and after a system reads a memory voltage value of memory information, an SVID command 'SetVID Fast XX' is sent to a corresponding VR address through a PCU unit inside a CPU and an SVID bus to achieve output voltage regulation of the corresponding VR. Under the condition that mainboard hardware and VR design are not changed in the SVID based memory voltage level bias testing method, level bias voltage regulation of the memory VR is achieved through SVID Command, the same system can conduct self-adaptive voltage regulation on memory voltage type (1.5V memory or 1.35V memory) inserted into a DIMM slot till a voltage level bias test value desirable by a user is reached, and the user can update BIOS version according to the testing conditions of an actual voltage level bias test. The SVID based memory voltage level bias testing method is simple and effectively meets the demand for memory voltage level bias testing of a server manufacturer in memory type selection and compatibility testing cases.

SVID based memory voltage level bias testing method

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SVID based memory voltage level bias testing method