A connecting device electrically connects a performance board which has PB terminals and a test head, and includes a sub board which is electrically connected to the test head and has sub terminals which face the PB terminals, a sealing mechanism which forms a sealed space between the sub board and the performance board, and a pressure reducing device which reduces the pressure of the sealed space. The pressure reducing device reduces the pressure of the sealed space so that the performance board and the sub board approach each other and the PB terminals and the sub terminals contact.

Connecting device, semiconductor wafer test apparatus comprising same, and connecting method

According to the present invention, disclosed is a semiconductor device having a test circuit. According to an embodiment of the present invention, the semiconductor device comprises: a test pad connected to a probe of test equipment during wafer test; a normal pad in which power or a signal is transmitted in a normal mode; and a test circuit which performs a predetermined test operation in accordance with a test signal applied through the test pad wherein the test circuit may be disposed at the bottom of the normal pad.

Semiconductor device having test circuit

A semiconductor device including a test circuit is disclosed. The semiconductor device includes a test pad coupled to a probe of a test device during a wafer test; a normal pad configured to receive a power or a signal during a normal mode; and a test circuit configured to perform a predetermined test operation based on a test signal received through the test pad. The test circuit is disposed below the normal pad.

Semiconductor device including test circuit

A test system for testing a plurality of semiconductor chips formed on a semiconductor wafer includes: a test wafer on which a plurality of test circuits corresponding to the plurality of semiconductor chips are formed, each test circuit testing a corresponding one of the plurality of semiconductor chips based on test data provided to the test circuit; where each of the plurality of test circuits includes a nonvolatile and rewritable pattern memory for storing the test data such as pattern data and sequence data, and the test system writes the same test data to all the plurality of test circuits in parallel.

Test system and write wafer

This invention relates to a test system that tests several semiconductor chips formed on a semiconductor wafer. The test system includes a testing wafer on which several test circuits are formed, wherein the several test circuits are disposed in accordance with the several semiconductor chips and test the corresponding semiconductor chips according to test data that is respectively given. Each of the test circuits has a non-volatile and rewritable pattern memory for storing test data such as pattern data and sequence data. The test system also has a control device, which parallelly writes same test data into each of the test circuits.

Test system and writing-in wafer

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Test system and write wafer

Test system and writing-in wafer