An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

Electrically erasable programmable read-only memory with NAND cell structure

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Atomic layer deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators

Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A storage capacitor is coupled to one of the first and the second source/drain regions. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.

DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators

A method of producing a MOS transistor of LDD structure with p(n) type pockets. A doped oxide film in which impurities such as phosphorus and impurities such as arsenic are doped is formed on a semiconductor substrate, and a nitride film is formed in regions where p type pockets are formed on the both sides of a gate electrode. By implementing heat treatment in the atmosphere of oxygen, the portion below the nitride film is placed in the condition where it is equivalent when heat treated in the atmosphere of nitrogen whereby a p type impurity region and an n - type impurity region are formed. The region except for that below the nitride film is heat treated in the atmosphere of oxygen to form an n + type impurity region. Further, with the gate electrode as a mask, n - type impurity region and p type impurity region are formed, thereafter selectively growing a film on the side walls of the gate electrode to form an n + type impurity region with the gate electrode and the film as masks, thus producing a MOS transistor.

Method of producing semiconductor device

A novel single-polysilicon EEPROM cell, called DIFLOX (diffused layer controlled floating-gate-type cell with thin oxide), has been used in this experimental memory. The floating-gate voltage is controlled by two thin-oxide capacitors coupled with two N/SUP +/ diffused layers: the drain and the control gate. Its size is reduced to 86.25 /spl mu/m/SUP 2/ by 1.2-/spl mu/m photolithography and scaled transistors with 1.4-/spl mu/m gate length. For programming time reduction, a page-mode programming scheme was used. Successive data of up to 16 bytes can be loaded into internal storage and programmed simultaneously. All high voltages needed to perform the ERASE/PROGRAM function are generated internally, and two kinds of timers were designed using an improved switched-capacitor technique. Owing to the open-bit-line scheme, cell data were detected with high sensitivity in spite of the large-bit-line and word-line parasitic capacitance. The EEPROM typically achieves a 150-ns address access time, with an 80-mW active and 1-/spl mu/W standby power dissipation. It was successfully fabricated in a single-polysilicon and single-metal CMOS process. The chip is 7.33/spl times/6.23 mm/SUP 2/ and is packed into the DIP 28 pin, which is pin-to-pin compatible to a 256-kb SRAM.

An experimental 5-V-only 256-kbit CMOS EEPROM with a high-performance single-polysilicon cell

Reliable CVD Inter-Poly Dielectrics for Advanced E&EEPROM

A semiconductor device is manufactured by forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type, and a first nonmonocrystalline silicon film is formed on the first insulating film. A second insulating film is deposited on the first nonmonocrystalline silicon film by CVD, sputtering or molecular beam method. An impurity is then ion-implanted in the first nonmonocrystalline silicon film through the second insulating film. The second insulating film is then removed to expose the surface of the first nonmonocrystalline silicon film doped with the impurity, and a thermal oxide film is formed on the exposed portion of the first nonmonocrystalline silicon film. Subsequently, a second nonmonocrystalline silicon film is formed on the thermal oxide film, and a third insulating film is formed on the second nonmonocrystalline silicon film.

Method of manufacturing SiO2 -Si interface for floating gate semiconductor device

A method for manufacturing a CMOS type semiconductor device is shown which includes the following steps. A first and a second conductive diffusion region are formed in a well region and a semiconductor substrate, respectively, and a gate electrode is formed thereon. An insulation layer is formed on the semiconductor substrate and the well region. A contact hole is opened by selectively removing the insulation layer corresponding to the first and the second conductive diffusion regions. At least one metal layer selected from a group consisting of metal and metal silicide having a high melting point is formed on an exposed surface of the first and the second conductive diffusion regions. The semiconductor substrate is heated to melt at least part of the insulation layer and form a tapered portion. A wiring layer is formed on the contact hole. This method prevents the contact resistance from increasing, the impurity of one region from diffusing into the other impurity regions, the impurity of the impurity regions from decreasing, and improves the reliability of the wiring layer by forming a tapered contact hole. These advantages permit high component density by miniaturizing the device.

Method for manufacturing a complementary MOS type semiconductor device

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