The invention discloses a method for network voltage amplitude, frequency and phase angle detection based on the one-phase phase-locked loop algorithm. According to the method, accurate amplitude, frequency and phase angle detection is achieved when direct current offset and harmonic waves exist in a one-phase power grid. The method comprises the steps that a network voltage signal is acquired and transmitted to a delay phase-shifting module; the delay phase-shifting module receives a network voltage frequency value obtained from the last cycle at the same time and outputs a network voltage delay signal; subtraction is carried out on the acquired network voltage signal and the network voltage delay signal to obtain a result, and the result is divided by 2 to obtain a network voltage signal free of direct current offset; the network voltage signal free of direct current offset is taken as an input signal of an enhanced phase-locked loop, and then the network voltage amplitude value, frequency value and phase angle value of the cycle are obtained. The method for network voltage amplitude, frequency and phase angle detection based on the one-phase phase-locked loop algorithm is suitable for the field of conversion of electrical energy.

Method for network voltage amplitude, frequency and phase angle detection based on one-phase phase-locked loop algorithm

Method for detecting phases of access point voltages of voltage source inverter by using three-phase software phase-locked loop

The present invention relates to a single phase voltage digital phase locking method, and a preset level signal similar to a voltage signal to be measured is constructed. In the control process, according to an angular frequency obtained by the accumulation of an incremental angular frequency outputted by a PI controller and a reference angular frequency, a preset frequency is adjusted; the phase difference component of level vectors corresponding to two voltage signals is controlled to approach 0; and when the control is stable, the phase of the signal to be measured is tracked by an outputted phase angle, and a phase locking function is completed. According to the present invention, the current sampling point of the voltage signal to be measured and a previous (k-n)th sampling point are used to form level vectors. In the control process, only n sampling points are needed to be kept; when n is equal to 1, only the sampling values of one sampling period are needed to be kept. The storage space occupied is very small, the calculation is convenient and practical, and the method can be applied to product development.

Single phase voltage digital phase locking method

The invention provides an inverter dead zone compensation system, which comprises a three-phase phaselocked loop, a first rotating conversion unit, a low-pass filter unit, and an inverted conversion unit, wherein the three-phase phaselocked loop is used for processing a three-phase current input into a motor to obtain a current angular frequency omega and a rotation angle theta; the first rotating conversion unit is used for performing the rotating conversion of the current according to the rotation angle theta to obtain a D axis current component and a Q axis current component; the low-pass filter unit is used for performing low-pass filtration on the D axis current component and the Q axis current component respectively; and the inverted conversion unit is used for performing inverted conversion on the D axis current component and the Q axis current component subjected to low-pass filtration and the current obtained after inverted conversion can be used directly for judging the zero crossing of the current in dead zone compensation. The invention also provides a corresponding method. According to the method, the angular frequency of the current is obtained by current sampling, so that the angular frequency of the three-phase current can be traced accurately at any time, and the judgment of the zero crossing of the current is always accurate.

Inverter dead zone compensation system and method

The invention provides a digital phase locking method suitable for a balanced three-phase power grid. The method comprises the following steps of: initializing the frequency of a first cyclic wave of A-phase power grid voltage ua to be 50Hz; setting the frequency of each of the other cyclic waves of ua to be the that of the last cyclic wave of ua, which is detected through a zero-crossing point detection circuit, and if the frequency is detected to be abnormal, transmitting a frequency failure alarming signal; and if the frequency is detected to be normal, performing multiplication between the frequency of a current cyclic wave of ua and the time Deltat of a corresponding counter and related simple operation to obtain a phase angle ThetaA of the A-phase power grid voltage ua and further obtain a phase angle ThetaABC of the balanced three-phase power grid. The digital phase locking method is quick, accurate, stable and reliable, and the dynamic by-the-cyclic-wave refreshing of the balanced three-phase power grid is realized.

Digital phase locking method suitable for balanced three-phase power grid

The invention discloses a balance error elimination type high-precision digital phase locking method. The method comprises the following steps of: (1) performing d and q coordinate transformation on a three-phase instantaneous sample value to obtain the ith phase of given phase value theta i; obtaining a phase difference signal delta (delta) v according to the given phase value theta i and a phase tracking output value theta v; locking the phase difference signal delta (delta) v into angular frequency omega of an input signal by using a PI regulator; and performing integration on the angular frequency omega to obtain the ith phase of phase angle Itheta1; (2) multiplying the ith phase of instantaneous sample value serving as the input signal by a sin (t) data pool and a cos (t) data pool to obtain Uin-sin (t) and Uin-cos (t) corresponding to the ith phase in the step (1) respectively; performing periodic averaging on the obtained results to obtain XC and YC respectively, wherein the phase angle IItheta2 of the ith phase is shown in the specification; and (3) performing weighted mean on the phase angle Itheta1 and the phase angle IItheta2 to obtain the final phase angle theta.

Balance error elimination type high-precision digital phase locking method

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Balance error elimination type high-precision digital phase locking method