A feedback loop is used to optimize a zero current threshold for a switching regulator. After the low side power switch of the switching regulator turns off, the switching node state is monitored to adjust the zero current threshold in a real time and thus the low-side power switch is prevented from turning off too early or too late. Thereby the efficiency in green mode is optimized.

Real time adjustable zero current detection for a switching regulator

Methods and apparatuses for a soft-start function with auto-disable are described. Such methods and apparatuses can gradually increase a voltage towards a reference voltage using a ramp generator and a control loop and can disable the ramp generator and the control loop once the voltage has reached the reference voltage.

Methods and Apparatuses for a Soft-Start Function with Auto-Disable

A DC-DC controller and an operation method thereof are provided. The DC-DC controller is configured to connect an output stage. The DC-DC controller includes a pulse width modulation (PWM) calculation circuit, a load transient detection circuit, and an override time calculation circuit. The PWM calculation circuit provides a PWM signal to the output stage. The load transient detection circuit receives an input signal related to an output voltage of the output stage. The load transient detection circuit provides a control signal according to the input signal and a predetermined input signal. The override time calculation circuit provides an override control signal with a predetermined time to the PWM calculation circuit according to the control signal. The PWM calculation circuit adjusts a duty cycle of the PWM signal according to the override control signal.

DC-DC controller and operation method thereof

Systems and methods for zero-current crossing detection circuits. In some embodiments, a circuit may include a buck converter comprising a high-side switch, a low-side switch, and an inductor; a zero-current crossing detection circuit comprising a reference switch coupled to a current source, where the reference switch is controllable conjointly with the low-side switch; an amplifier coupled to: (a) a first node between the current source and reference switch, where in operation the first node has a positive voltage value during an interval of interest, and a (b) second node between the low-side switch and the inductor, where in operation the second node has a negative voltage value during the interval of interest; and a comparator coupled to the amplifier, the comparator configured to output a flag in response to a detection that a decreasing current through the inductor has reached a predetermined value.

Zero-current crossing detection circuits

A voltage regulator compensation circuit provides power to a dynamic load and includes a power transistor configured to drive the dynamic load, a reference determining transistor configured to establish a voltage reference proportional to a regulated output voltage of the power transistor, and a control circuit coupled to a gate input of both the power transistor and the reference determining transistor. Also included is a comparison engine configured to compare the regulated output voltage and the voltage reference, and a current consuming transistor operatively coupled to an output of the power transistor and configured to provide a varying secondary load. The comparison engine is configured to control the current consuming transistor to increase current draw or decrease current draw from the power transistor based on the difference between the regulated output voltage and the voltage reference.

Method and apparatus for optimizing linear regulator transient performance

A DC-DC converter has high-side power and low-side power transistors connected in series between supply terminals, an inductor connected between the power transistors and an output terminal. A comparator compares the output voltage with a reference voltage. A detector detects when inductor current approaches zero. A timer is configured to determine a minimum ON time of the high-side power transistor optimized for a particular value inductor. A current detector detects current flow in the back-gate diode of the low-side power transistor. timer is configured to determine an overriding ON time in response to the back-gate current detector. Logic provides control signals to gate power transistors in response to the comparator and the longer one of the minimum ON time and the overriding ON time. The minimum ON time for the high-side power transistor is adjusted in response to the actual inductance of the inductor.

DC-DC converter with automatic inductor detection for efficiency optimization

A level shifter circuit has a plurality of channels for providing signals to a capacitive load and has circuits for sharing charge stored in the capacitive load between the channels. A first pair of channel clock generating circuits are coupled respectively to a first pair of channels. A second pair of channel clock generating circuits are coupled respectively to a second pair of channels. A pair of switches couple the first pair of channels together and the second pair of channels together, respectively, for sharing charge between the channels. A single resistor is coupled in circuit with all of the channels for controlling a slope of charge sharing between channels.

Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching

DC-DC-Wandler mit einem High-Side-Leistungstransistor und einem Low-Side-Leistungstransistor, die zwischen Versorgungsanschlussen in Reihe geschaltet sind. Eine Induktivitat ist zwischen einem Verbindungsknoten der Leistungstransistoren und einem Ausgangsanschluss, mit dem eine Last verbunden ist ist, geschaltet. Ein Komparator vergleicht die Ausgangsspannung am Ausgangsanschluss mit einer Referenzspannung. Ein Induktivitatsstromdetektor detektiert, wenn sich der Induktivitatsstrom Null nahert. Ein Zeitgeber fur eine Mindesteinschaltzeit ist so ausgefuhrt, dass er eine Mindesteinschaltzeit des High-Side-Leistungstransistors bestimmt, die fur einen bestimmten Wert der Induktivitat optimiert ist. Ein Backgate-Stromdetektor detektiert den Stromfluss in der Backgate-Diode des Low-Side-Leistungstransistors. Ein Vorrang-Zeitgeber ist so ausgefuhrt, dass er in Reaktion auf den Backgate-Stromdetektor eine vorrangige Einschaltzeit bestimmt. Eine Steuerlogik stellt in Reaktion auf eine Ausgabe des Komparators und in Reaktion auf die jeweils langere Zeit der Mindesteinschaltzeit und der vorrangigen Einschaltzeit Steuersignale fur Gatetreiber fur die Leistungstransistoren bereit. Die Mindesteinschaltzeit fur den High-Side-Leistungstransistor wird in Reaktion auf den Induktivitatswert der jeweils angeschlossenen Induktivitat eingestellt. Dementsprechend wird die Mindesteinschaltzeit fur grosere Induktivitatswerte automatisch verlangert, wodurch die Wandlereffizienz bei geringem Laststrom verbessert wird.

DC-DC-Wandler mit automatischer Induktivitätserfassung zur Effizienzoptimierung

In described examples, a level shifter circuit (700) has a plurality of channels (706, 714, 722, 724) for providing signals to a capacitive load and has circuits (M3a, M3b, M3c, M3d) for sharing charge stored in the capacitive load between the channels (706, 714, 722, 724). A first pair of channel clock generating circuits (Mia, M2a, M1b, M2b) are coupled respectively to a first pair of channels (706, 722). A second pair of channel clock generating circuits (M1c, M2c, Mid, M2d) are coupled respectively to a second pair of channels (714, 724). A first pair of switches (M3a, M3b) couples the first pair of channels (706, 722) together, and a second pair of switches (M3c, M3d) couples the second pair of channels (714, 724) together, for sharing charge between the channels (706, 714, 722, 724). A single resistor (Res) is coupled in circuit with all of the channels (706, 714, 722, 724) for controlling a slope of charge sharing between the channels (706, 714, 722, 724).

Level shifter for a liquid crystal display

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DC-DC converter with automatic inductor detection for efficiency optimization

Cost effective low pin/ball count level-shifter for LCD bias applications supporting charge sharing of gate lines with perfect waveform matching

DC-DC-Wandler mit automatischer Induktivitätserfassung zur Effizienzoptimierung

Level shifter for a liquid crystal display