Ideas which have origins in Shannon's work in information theory have arisen independently in a mathematical discipline called symbolic dynamics. These ideas have been refined and developed in recent years to a point where they yield general algorithms for constructing practical coding schemes with engineering applications. In this work we prove an extension of a coding theorem of Marcus and trace a line of mathematics from abstract topological dynamics to concrete logic network diagrams.

/pdf/algorithms-for-sliding-block-codes-an-application-of-2y1osguoni.pdf

Algorithms for sliding block codes---An application of symbolic dynamics to information theory

Runlength-limited (RLL) sequences are formally defined, and the runlength distribution and spectral properties of ideal RLL sequences are analyzed. A detailed description is furnished of the limiting properties of RLL sequences, and a comprehensive review is given of the practical aspects involved in the translation of arbitrary data into RLL sequences. Examples of code implementation are presented to illustrate the variety of possible design tools. >

Runlength-limited sequences

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Semiconductor memory device and method of controlling the same

A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized.

System and method for efficient uncorrectable error detection in flash memory

A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery. Various embodiments, including an embodiment incorporating the analog functions as well as the primary digital functions of the read channel in a single integrated circuit, and preferred embodiments utilizing a reduced complexity, programmable modified Viterbi detector supporting a broad class of partial response channels are disclosed.

Synchronous read channel

Apparatus for converting binary digital data from one form to another according to a variable word length code of fixed rate comprises word position indicating circuitry for indicating predetermined word position states of data in a data storage unit and conversion circuitry for sequentially converting a constant number of input bits at a time into the corresponding number of bits in said other form in dependence upon the contents of the data storage unit and the word position indication. The constant number of bits is less than the number of bits in the longest variable length word in the input data code form. The word position indicating circuitry either generates an updated function representing the current position of the word boundary in the data storage unit or recognizes the boundary from distinctive word ending patterns in the data storage unit.

Sequential encoding and decoding of variable word length, fixed rate data codes

A method for correcting error bursts in data which are uncorrectable by an ECC in a communications channel in which no pointer is available or if available is not generated. The data is recorded in blocks preferably comprising subblocks. Parity cell syndromes are generated for each block during writing; and during reading these syndromes are analyzed to identify possible starting points of error burst locations. A trial correction is applied to the data in the uncorrectable block (or subblock), then verified whether successful using CRC. The correction is accepted as valid if and only if only one trial correction is verified as successful. The maximum number B of consecutive bytes in error correctable in a block is less than, the number N of bytes in each parity cell, and N-B is selected to limit the probability of miscorrection.

Abbreviated trial-and-error technique for correcting long bursts of consecutive errors using CRC bytes

Thin magnetic film

A data processing system and method providing error protection for data transmitted between a processor and a buffer in one data format and transmitted between the buffer and a user device in a different data format. An adaptor is interposed between the processor and the buffer for transmitting to the buffer (i) successive data segments in the one data format, each ending with appended check bytes in a preselected cyclic redundancy code (CRC); and (ii) check bytes using the same CRC appended at the end of each segment in the different data format to create in the buffer records which are a composite of both formats, but viewed as in the one data format by the processor and as in the different data format by the user device. The boundaries of the segments in each format must be known to the adaptor. Since both formats use the same CRC, CRC bytes for each segment in each data format will provide an identical preselected value in the absence of a detectable error. A second adaptor, which does not and need not know the boundaries of the data segments in the one data format, is interposed between the buffer and the user device for transmitting the data between the buffer and user device in the different data format.

Common error protection code for data stored as a composite of different data formats

Isotropic thin magnetic film

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